SC28L194A1A-S NXP Semiconductors, SC28L194A1A-S Datasheet - Page 21

• Manufacturer Part Number: SC28L194A1A-S
• Manufacturer: NXP Semiconductors

Specifications of SC28L194A1A-S

• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Supply Current: 30mA
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
00110
00111
01000
01001
01010
01011
01100
01101
01111
10000
10001
10010
10011
2006 Aug 15
Quad UART for 3.3 V and 5 V supply voltage
Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active, the
break begins when transmission of the current character
is completed. If there are characters in the TxFIFO, the
start of break is delayed until those characters, or any
others loaded after it have been transmitted (TxEMT must
be true before break begins). The transmitter must be
enabled to start a break.
Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the
next character, if any, is transmitted.
Assert RTSN. Causes the RTSN output to be asserted
(low).
Negate RTSN. Causes the RTSN output to be negated
(high).
Note: The two commands above actually reset and
set, respectively, the I/O2 or I/O1 pin associated with
the I/OPIOR register.
Reserved.
Reserved.
Reserved.
Block error status mode. Upon reset of the device or an
individual receiver, the block mode of receiver error status
accumulates as each character moves to the bottom of
the RxFIFO, the position from which it will be read. In this
mode of operation, the RxFIFO may contain a character
with non-zero error status for some time. The status will
not reflect the error character’s presence until it is ready to
be popped from the RxFIFO. Command 01101 allows the
error status to be updated as each character is pushed
into the RxFIFO. This allows the earliest detection of a
problem character, but complicates the determination of
exactly which character is causing the error. This mode of
block error accumulation may be exited only by resetting
the chip or the individual receiver.
Reserved.
Transmit an Xon Character
Transmit an Xoff Character
Reserved for channels b-d, for channel a: enables a Gang
Write of Xon Character Registers. After this command is
issued, a write to the channel A Xon Character Register
will result in a write to all channel’s Xon character
registers. This command provides a mechanism to
initialize all the Xon Character registers with one write. A
write to channel A Xon Character Register returns the
Quad UART to the individual Xon write mode.
Reserved for channels b-d, for channel a: enables Gang
Write of Xoff Character Registers. After this command is
issued, a write to the channel A Xoff Character Register
will result in a write to all channel’s Xoff character
registers. This command provides a mechanism to
initialize all the Xoff Character registers with one write. A
write to channel A Xoff Character Register returns the
Quad UART to the individual Xoff write mode.
21
Note: Gang writing of Xon/Xoff Character Commands: Issuing
command causes the next write to Xon/Xoff Character Register
A to effect a simultaneous write into the other 3 Xon/Xoff
character registers. After the Xon/Xoff Character Register A is
written, the 28L194 returns to individual write mode for the
Xon/Xoff Character Registers. Other intervening reads and
writes are ignored. The device resets to individual write mode.
10100
10101
10110
10111
11000
11001-11011
11011
11100-11101
11110
11111
Reserved for channels b-d, for channel a: executes a
Gang Load of Xon Character Registers. Executing this
command causes a write of the value x’11 to all channel’s
Xon character registers. This command provides a
mechanism to initialize all the Xon Character registers to a
default value with one write. Execution of this command is
immediate and does not effect the timing of subsequent
host I/O operations.
Reserved for channels b-d, for channel a: executes a
Gang Load of Xoff Character Registers. Executing this
command causes a write of the value x’13 to all channel’s
Xoff character registers. This command provides a
mechanism to initialize all the Xoff Character registers to a
default value with one write. Execution of this command is
immediate and does not effect the timing of subsequent
host I/O operations.
Xoff resume command (CRXoffre; not active in
“Auto-Transmit Mode”). A command to cancel a previous
Host Xoff command. Upon receipt, the channel’s
transmitter will transfer a character, if any, from the
TxFIFO and begin transmission.
Host Xoff command (CRXoff). This command allows tight
host CPU control of the flow control of the channel
transmitter. When interrupted for receipt of an Xoff
character by the receiver, the host may stop transmission
of further characters by the channel transmitter by issuing
the Host Xoff command. Any character that has been
transferred to the TxD shift register will complete its
transmission, including the stop bit.
Cancel Host transmit flow control command. Issuing this
command will cancel a previous transmit command if the
flow control character is not yet loaded into the TxD Shift
Register. If there is no character waiting for transmission
or if its transmission has already begun, then this
command has no effect.
Reserved.
Reset Address Recognition Status. This command clears
the interrupt status that was set when an address
character was recognized by a disabled receiver
operating in the special mode.
Reserved.
Resets all UART channel registers. This command
provides a means to zero all the UART channels that are
not reset to x’00 by a reset command or a hardware reset.
Reserved for channels b-d, for channel a: executes a chip
wide reset. Executing this command in channel a is
equivalent to a hardware reset with the RESETN pin.
Executing command register reset in channel b-d, has no
effect.
SC28L194
Product data sheet