ISP1505ABS-S NXP Semiconductors, ISP1505ABS-S Datasheet - Page 48
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ISP1505ABS-S
Manufacturer Part Number
ISP1505ABS-S
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1505ABS-S.pdf
(76 pages)
Specifications of ISP1505ABS-S
Number Of Transceivers
1
Esd Protection
YeskV
Operating Supply Voltage (typ)
Not RequiredV
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
Table 28.
Table 29.
ISP1505A_ISP1505C_3
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
USE_EXT_VBUS_
IND
DRV_VBUS_EXT
DRV_VBUS
CHRG_VBUS
DISCHRG_VBUS
DM_PULLDOWN
DP_PULLDOWN
-
OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description
USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit
allocation
10.1.5 USB Interrupt Enable Rising Edge register
R/W/S/C
7
0
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all
transitions are enabled.
Description
Use External V
0b — Use the internal OTG comparator.
1b — Use the external V
Drive V
0b — Do not drive PSW_N to LOW, disabling V
1b — Drive PSW_N to LOW, enabling V
Drive V
then setting DRV_VBUS is optional.
Charge V
first check that V
DM data lines have been LOW (SE0) for 2 ms.
0b — Do not charge V
1b — Charge V
Discharge V
for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0
to stop the discharge.
0b — Do not discharge V
1b — Discharge V
DM Pull Down: Enables the 15 k pull-down resistor on DM.
0b — Pull-down resistor is not connected to DM.
1b — Pull-down resistor is connected to DM.
DP Pull Down: Enables the 15 k pull-down resistor on DP.
0b — Pull-down resistor is not connected to DP.
1b — Pull-down resistor is connected to DP.
reserved; writing logic 1 will give undefined results
R/W/S/C
6
0
BUS
BUS
reserved
BUS
: Signals the ISP1505 to drive 5 V on V
External: Controls the external V
BUS
: Charges V
R/W/S/C
BUS
BUS
BUS
: Discharges V
BUS
5
0
.
Indicator: Informs the PHY to use an external V
is discharged (see the DISCHRG_VBUS bit), and that both the DP and
Rev. 03 — 26 August 2008
.
BUS
Table 29
BUS
BUS
BUS
.
R/W/S/C
valid indicator signal input from the FAULT pin.
.
through a resistor. Used for the V
BUS
4
1
shows the bit allocation of the register.
through a resistor. If the link sets this bit to logic 1, it waits
BUS
ULPI HS USB host and peripheral transceiver
R/W/S/C
END_R
SESS_
.
BUS
3
1
ISP1505A; ISP1505C
BUS
supply through the RESET_N/PSW_N pin.
BUS
.
. If DRV_VBUS_EXT is set to logic 1,
VALID_R
R/W/S/C
SESS_
2
1
BUS
pulsing SRP. The link must
BUS
VALID_R
R/W/S/C
VBUS_
overcurrent indicator.
1
1
© NXP B.V. 2008. All rights reserved.
DISCON_R
R/W/S/C
HOST_
0
1
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