ISP1507EBSUM STEricsson, ISP1507EBSUM Datasheet - Page 17

• Manufacturer Part Number: ISP1507EBSUM
• Manufacturer: STEricsson

Specifications of ISP1507EBSUM

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 6.
CD00222691
Product data sheet
Signal
TX_ENABLE
DAT
SE0
INT
Signal mapping for 3-pin serial mode
8.1.3 3-pin full-speed or low-speed serial mode
8.2 USB and OTG state transitions
Maps to
DATA0
DATA1
DATA2
DATA3
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in
3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see
3-pin serial mode, the link asserts STP. This is primarily provided for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as
defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the
USB 2.0 Specification Rev. 1.3. The ISP1507 accommodates various states through
register bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0],
DP_PULLDOWN and DM_PULLDOWN.
Table 7
resistor settings as also given in
The link is responsible for setting the desired USB and OTG states.
•
•
•
•
RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP
RPD_DP_EN enables the 15 kΩ pull-down resistor on DP
RPD_DM_EN enables the 15 kΩ pull-down resistor on DM
HSTERM_EN enables the 45 Ω termination resistors on DP and DM
summarizes operating states. The values of register settings in
O
Direction
I
I/O
I/O
Description
active HIGH transmit enable
transmit differential data on DP and DM when TX_ENABLE is HIGH
receive differential data from DP and DM when TX_ENABLE is LOW
transmit single-ended zero on DP and DM when TX_ENABLE is HIGH
receive single-ended zero from DP and DM when TX_ENABLE is LOW
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
Rev. 04 — 20 May 2010
Table
Table
7. Resistor setting signals are defined as follows:
6. To enter 3-pin serial mode, the link sets the
ISP1507E; ISP1507F
Section
ULPI HS USB OTG transceiver
10.1.3) to logic 1. To exit
© ST-ERICSSON 2010. All rights reserved.
Table 7
will force
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