ISP1507EBSUM STEricsson, ISP1507EBSUM Datasheet - Page 73

• Manufacturer Part Number: ISP1507EBSUM
• Manufacturer: STEricsson

Specifications of ISP1507EBSUM

• Lead Free Status / RoHS Status: Supplier Unconfirmed

21. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. RXCMD byte format . . . . . . . . . . . . . . . . . . . .25
Table 11. LINESTATE[1:0] encoding for upstream facing
Table 12. LINESTATE[1:0] encoding for downstream facing
Table 13. Encoded V
Table 14. V
Table 15. Encoded USB event signals . . . . . . . . . . . . . .28
Table 16. PHY pipeline delays . . . . . . . . . . . . . . . . . . . .32
Table 17. Link decision times . . . . . . . . . . . . . . . . . . . . .33
Table 18. Immediate register set overview . . . . . . . . . . .45
Table 19. Extended register set overview . . . . . . . . . . . .45
Table 20. VENDOR_ID_LOW - Vendor ID Low register
Table 21. VENDOR_ID_HIGH - Vendor ID High register
Table 22. PRODUCT_ID_LOW - Product ID Low register
Table 23. PRODUCT_ID_HIGH - Product ID High register
Table 24. FUNC_CTRL - Function Control register (address
Table 25. FUNC_CTRL - Function Control register (address
Table 26. INTF_CTRL - Interface Control register (address
Table 27. INTF_CTRL - Interface Control register (address
Table 28. OTG_CTRL - OTG Control register (address R =
Table 29. OTG_CTRL - OTG Control register (address R =
Table 30. USB_INTR_EN_R_E - USB Interrupt Enable
Table 31. USB_INTR_EN_R_E - USB Interrupt Enable
Table 32. USB_INTR_EN_F_E - USB Interrupt Enable
CD00222691
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 3-pin serial mode . . . . . . .17
Operating states and their corresponding resistor
settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
OTG_CTRL register power control bits . . . . . .24
TXCMD byte format . . . . . . . . . . . . . . . . . . . . .24
ports: peripheral . . . . . . . . . . . . . . . . . . . . . . . .26
ports: host . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
applications . . . . . . . . . . . . . . . . . . . . . . . . . . .27
(address R = 00h) bit description . . . . . . . . . . .46
(address R = 01h) bit description . . . . . . . . . . .46
(address R = 02h) bit description . . . . . . . . . . .46
(address R = 03h) bit description . . . . . . . . . . .46
R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . .49
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit description . .50
BUS
indicators in RXCMD required for typical
BUS
voltage state . . . . . . . . . . . . . .26
Rev. 04 — 20 May 2010
Table 33. USB_INTR_EN_F_E - USB Interrupt Enable
Table 34. USB_INTR_STAT - USB Interrupt Status register
Table 35. USB_INTR_STAT - USB Interrupt Status register
Table 36. USB_INTR_L - USB Interrupt Latch register
Table 37. USB_INTR_L - USB Interrupt Latch register
Table 38. DEBUG - Debug register (address R = 15h) bit
Table 39. DEBUG - Debug register (address R = 15h) bit
Table 40. SCRATCH - Scratch register (address R = 16h to
Table 41. PWR_CTRL - Power Control register (address
Table 42. PWR_CTRL - Power Control register (address
Table 43. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 44. Recommended operating conditions . . . . . . . 55
Table 45. Static characteristics: supply pins . . . . . . . . . . 56
Table 46. Static characteristics: digital pins (CLOCK, DIR,
Table 47. Static characteristics: digital pin FAULT . . . . . 57
Table 48. Static characteristics: analog I/O pins
Table 49. Static characteristics: charge pump . . . . . . . . 59
Table 50. Static characteristics: V
Table 51. Static characteristics: V
Table 52. Static characteristics: ID detection circuit . . . . 59
Table 53. Static characteristics: resistor reference . . . . . 60
Table 54. Dynamic characteristics: reset and clock . . . . 61
Table 55. Dynamic characteristics: digital I/O pins . . . . . 62
Table 56. Dynamic characteristics: analog I/O pins (DP and
Table 57. Recommended list of materials . . . . . . . . . . . . 65
Table 58. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 59. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 72
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit allocation . . . . 50
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit description . . . 50
(address R = 13h) bit allocation . . . . . . . . . . . 51
(address R = 13h) bit description . . . . . . . . . . 51
(address R = 14h) bit allocation . . . . . . . . . . . 51
(address R = 14h) bit description . . . . . . . . . . 51
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
18h, W = 16h, S = 17h, C = 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STP, NXT, DATA[3:0], RESET_N/PSW_N) . . . 56
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ISP1507E; ISP1507F
ULPI HS USB OTG transceiver
BUS
BUS
© ST-ERICSSON 2010. All rights reserved.
comparators . . . . 59
resistors . . . . . . . . 59
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