ISP1507DBS-T NXP Semiconductors, ISP1507DBS-T Datasheet - Page 48

• Manufacturer Part Number: ISP1507DBS-T
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507DBS-T

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: ISP1507DBS,518

NXP Semiconductors
Table 27.
Table 28.
ISP1507C_ISP1507D_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7
6
5
4
3
2
1
0
Symbol
USE_EXT_
VBUS_IND
DRV_VBUS_EXT
DRV_VBUS
CHRG_VBUS
DISCHRG_VBUS
DM_PULLDOWN
DP_PULLDOWN
-
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation
OTG_CTRL - OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description
USE_EXT_
VBUS_IND
10.1.4 OTG_CTRL register
10.1.5 USB_INTR_EN_R_E register
R/W/S/C
7
0
This register controls various OTG functions of the ISP1507. The bit allocation of the
OTG_CTRL register is given in
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all
transitions are enabled.
VBUS_EXT
Description
Use External V
0b — Use the internal OTG comparator.
1b — Use the external V
Drive V
0b — Do not drive PSW_N to LOW, disabling V
1b — Drive PSW_N to LOW, enabling V
Drive V
then setting DRV_VBUS is optional.
Charge V
first check that V
DM data lines have been LOW (SE0) for 2 ms.
0b — Do not charge V
1b — Charge V
Discharge V
for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0
to stop the discharge.
0b — Do not discharge V
1b — Discharge V
DM Pull Down: Enables the 15 k pull-down resistor on DM.
0b — Pull-down resistor is not connected to DM.
1b — Pull-down resistor is connected to DM.
DP Pull Down: Enables the 15 k pull-down resistor on DP.
0b — Pull-down resistor is not connected to DP.
1b — Pull-down resistor is connected to DP.
reserved; writing logic 1 will give undefined results
R/W/S/C
DRV_
6
0
BUS
BUS
BUS
: Signals the ISP1507 to drive 5 V on V
External: Controls the external V
BUS
: Charges V
R/W/S/C
BUS
BUS
DRV_
VBUS
BUS
: Discharges V
BUS
5
0
.
Indicator: Informs the PHY to use an external V
is discharged (see the DISCHRG_VBUS bit), and that both the DP and
.
BUS
Rev. 01 — 28 May 2008
Table 29
BUS
BUS
BUS
.
R/W/S/C
valid indicator signal input from the FAULT pin.
.
CHRG_
through a resistor. Used for the V
VBUS
Table
BUS
4
0
shows the bit allocation of the register.
through a resistor. If the link sets this bit to logic 1, it waits
27.
BUS
DISCHRG_
ULPI HS USB host and peripheral transceiver
R/W/S/C
.
VBUS
BUS
3
0
ISP1507C; ISP1507D
BUS
supply through the RESET_N/PSW_N pin.
BUS
.
. If DRV_VBUS_EXT is set to logic 1,
DM_PULL
R/W/S/C
DOWN
2
1
BUS
pulsing SRP. The link must
BUS
DP_PULL
R/W/S/C
DOWN
overcurrent indicator.
1
1
© NXP B.V. 2008. All rights reserved.
reserved
R/W/S/C
0
0
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