ADV7190KST Analog Devices Inc, ADV7190KST Datasheet - Page 29
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ADV7190KST
Manufacturer Part Number
ADV7190KST
Description
Manufacturer
Analog Devices Inc
Datasheet
1.ADV7190KST.pdf
(72 pages)
Specifications of ADV7190KST
Number Of Dac's
6
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LQFP
Pin Count
64
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADV7190KST
Manufacturer:
ADI
Quantity:
642
Part Number:
ADV7190KST
Manufacturer:
ADI/亚德诺
Quantity:
20 000
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 50 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR00–MR01)
These bits are used to set up the encoder mode. The ADV7190/
ADV7191 can be set up to output NTSC, PAL (B, D, G, H, I),
PAL M or PAL N standard video.
Luminance Filter Select (MR02–MR04)
These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Select (MR05–MR07)
These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cut-off frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or
QCIF filters.
REV. B
MR07 MR06 MR05
0
0
0
0
1
1
1
1
BE WRITTEN
ZERO MUST
TO THIS BIT
MR16
MR17
MR17
0
1
0
0
1
1
0
0
1
1
MR07
4
CHROMA FILTER SELECT
2
4
OVERSAMPLING
0
1
0
1
0
1
0
1
CONTROL
OVERSAMPLING
OVERSAMPLING
1.3 MHz LOW-PASS FILTER
0.65 MHz LOW-PASS FILTER
1.0 MHz LOW-PASS FILTER
2.0 MHz LOW-PASS FILTER
RESERVED
CIF
QCIF
3.0 MHz LOW-PASS FILTER
MR16
MR06
MR15
0
1
DAC CONTROL
POWER-DOWN
NORMAL
Figure 50. Mode Register 0 (MR0)
Figure 51. Mode Register 1 (MR1)
DAC A
MR15
MR05
MR14
MR04 MR03 MR02
0
1
0
0
0
0
1
1
1
1
DAC CONTROL
POWER-DOWN
NORMAL
DAC B
MR14
0
0
1
1
0
0
1
1
MR04
MR13
LUMA FILTER SELECT
0
1
0
1
0
1
0
1
0
1
–29–
DAC CONTROL
POWER-DOWN
NORMAL
LOW-PASS FILTER (NTSC)
LOW-PASS FILTER (PAL)
NOTCH FILTER (NTSC)
NOTCH FILTER (PAL)
EXTENDED MODE
CIF
QCIF
RESERVED
MR13
DAC C
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 51 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR10–MR15)
Bits MR15–MR10 can be used to power down the DACs. This is
used to reduce the power consumption of the ADV7190/ADV7191
or if any of the DACs are not required in the application.
4 Oversampling Control (MR16)
To enable 4¥ Oversampling this bit has to be set to 1. When
enabled, the data is output at a frequency of 54 MHz.
Note that PLL Enable Control has to be enabled (MR61 = 0) in
4¥ Oversampling mode.
Reserved (MR17)
A Logical 0 must be written to this bit.
MR03
MR12
0
1
DAC CONTROL
POWER-DOWN
NORMAL
MR12
DAC D
MR02
MR01 MR00
MR11
0
0
1
1
0
1
DAC CONTROL
STANDARD SELECTION
0
1
0
1
POWER-DOWN
NORMAL
DAC E
MR11
MR01
OUTPUT VIDEO
NTSC
PAL (B, D, G, H, I)
PAL (M) (ADV7190 ONLY)
PAL (N)
MR10
0
1
DAC CONTROL
POWER-DOWN
NORMAL
MR10
DAC F
MR00
ADV7190/ADV7191