ADV7190KST Analog Devices Inc, ADV7190KST Datasheet - Page 32

• Manufacturer Part Number: ADV7190KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7190KST

• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

ADV7190/ADV7191
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninter-
laced mode.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 55 shows
the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the component Y output level on the ADV7190/
ADV7191. If this bit is set (0), the encoder outputs Betacam
levels when configured in PAL or NTSC mode. If this bit is
set (1), the encoder outputs SMPTE levels when configured
in PAL or NTSC mode.
UV-Levels Control (MR51–MR52)
These bits control the component U and V output levels on
the ADV7190/ADV7191. It is possible to have UV levels with
a peak-to-peak amplitude of either 700 mV (MR52 + MR51
= 01 ) or 1000 mV (MR52 + MR51 = 10) in NTSC and PAL.
MR47
0
1
MR57
MODE CONTROL
INTERLACED
0
1
INTERLACED
NONINTERLACED
POSITION
FRONT PORCH
BACK PORCH
CLAMP
MR57
MR47
MR46
0
1
MR56
COLOR BAR
CONTROL
CLAMP DELAY
0
1
DISABLE
ENABLE
DIRECTION
MR56
POSITIVE
NEGATIVE
MR46
MR45
0
1
MR55 MR54
Figure 55. Mode Register 5 (MR5)
Figure 54. Mode Register 4 (MR4)
0
0
1
1
CONTROL
ENABLE BURST
DISABLE BURST
BURST
MR55
CLAMP DELAY
MR45
0
1
0
1
MR44
0
1
CHROMINANCE
NO DELAY
1
2
3
ENABLE COLOR
DISABLE COLOR
CONTROL
MR54
PCLK
PCLK
PCLK
MR44
–32–
MR43
MR53
0
1
0
1
RGB SYNC
It is also possible to have default values of 934 mV for NTSC
and 700 mV for PAL (MR52 + MR51 = 00).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay Value (MR54–MR55)
These bits control the delay or advance of the CLAMP signal
in the front or back porch of the ADV7190/ADV7191. It is
possible to delay or advance the pulse by zero, one, two, or
three clock cycles.
Note: Pin 51 is a multifunctional pin (VSO/CLAMP). CLAMP/
VSO Select Control (MR77) has to be set accordingly.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP
signal. If this bit is set (1), the delay is negative. If it is set (0),
the delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (1), the CLAMP signal is located in the back porch position.
If this bit is set (0), the CLAMP signal is located in the front
porch position.
720 PIXELS
710 PIXELS/702 PIXELS
MR53
LINE DURATION
ACTIVE VIDEO
DISABLE
ENABLE
MR43
MR52 MR51
0
0
1
1
MR42 MR41
0
0
1
1
UV LEVEL CONTROL
MR52
0
1
0
1
MR42
GENLOCK CONTROL
0
1
0
1
DEFAULT LEVELS
700mV
1000mV
RESERVED
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
TIMING RESET
ENABLE RTC PIN
MR51
MR41
MR50
0
1
VSYNC 3H CONTROL
MR40
CONTROL
Y LEVEL
0
1
MR50
DISABLE
ENABLE
MR40
DISABLE
ENABLE
REV. B