SAA7129HV1 NXP Semiconductors, SAA7129HV1 Datasheet - Page 23

• Manufacturer Part Number: SAA7129HV1
• Manufacturer: NXP Semiconductors

Specifications of SAA7129HV1

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14325
Product data sheet
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Bit
7 to 0
Bit
7
6
5
4
3
2
1
0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Symbol
VPS5[7:0]
Symbol
VPS11[7:0] eleventh byte of video programming system data in line 16; LSB first
Symbol
VPS12[7:0] twelfth byte of video programming system data in line 16; LSB first
Symbol
VPS13[7:0] thirteenth byte of video programming system data in line 16; LSB first
Subaddress 53h
Subaddress 54h
Subaddress 55h
Subaddress 56h
Subaddress 57h
Subaddress 58h
Symbol
LUTY[7:0] LUT for the color values inserted in case of key color 2 Y detection in the
Symbol
VPSEN
-
ENCIN
RGBIN
DELIN
VPSEL
EDGE2
EDGE1
Rev. 03 — 9 December 2004
Description
MPEG input data stream; LUTY[7:0] = 80h; default value after reset
Description
0 = video programming system data insertion is disabled; default state
after reset,
1 = video programming system data insertion in line 16 is enabled.
this bit is not used and should be set to logic 0
0 = encoder path is fed with MP
state after reset,
1 = encoder path is fed with output signal of fader; see
0 = RGB path is fed with MP
after reset,
1 = RGB path is fed with output signal of fader; see
0 = not supported in current version; do not use,
1 = recommended value; default state after reset.
0 = not supported in current version; do not use,
1 = recommended value; default state after reset.
0 = MP
reset,
1 = MP
0 = MP
reset,
1 = MP
Description
fifth byte of video programming system data in line 16; LSB first
Description
Description
Description
B
B
A
A
data is sampled on the rising clock edge; default state after
data is sampled on the falling clock edge.
data is sampled on the rising clock edge; default state after
data is sampled on the falling clock edge.
SAA7128H; SAA7129H
B
input data; fader is bypassed; default state
B
input data; fader is bypassed; default
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Digital video encoder
Section
Section
7.1.
7.1.
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