SAA7120H/V2,557 NXP Semiconductors, SAA7120H/V2,557 Datasheet - Page 8

• Manufacturer Part Number: SAA7120H/V2,557
• Manufacturer: NXP Semiconductors

Specifications of SAA7120H/V2,557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
7.2.2
Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. At each rising edge of output
signal (TTXRQ) a single teletext bit has to be provided
after a programmable delay at the input pin.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set to
360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.10.
7.2.3
Using this circuit, data in accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
The actual line number where data is to be encoded in, can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.
7.2.4
For more information contact your nearest Philips
Semiconductors sales office.
7.3
In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitude at the input of
the DAC for CVBS is reduced by
Y and C DACs to make maximum use of conversion
ranges.
2002 Oct 11
Digital video encoder
Output interface/DACs
T
C
A
ELETEXT INSERTION AND ENCODING
NTI
LOSED CAPTION ENCODER
-
TAPING
(SAA7120H
15
ONLY
16
with respect to
)
8
Outputs of the DACs can be set together in two groups, via
software control, to a minimum output voltage for either
purpose.
7.4
The synchronization of the SAA7120H; SAA7121H is able
to operate in two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and the on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it also can be used to set the horizontal phase.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be applied to pin RCV2. Timing
and trigger behaviour can also be influenced for the signal
at pin RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time
base of the IC runs free, thus an arbitrary number of
synchronization slopes may miss, but no additional pulses
(with the incorrect phase) must occur.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Alternatively, the device can be triggered by auxiliary
codes in a “CCIR 656” data stream at the MP port.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the device can
output:
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The polarity of both RCV1 and RCV2 is selectable by
software control.
The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
A Vertical Sync (VS) signal with 3 or 2.5 lines duration
An odd/even signal which is LOW in odd fields
A Field Sequence (FSEQ) signal which is HIGH in the
first of 4 or 8 fields respectively.
Synchronization
SAA7120H; SAA7121H
Product specification