SAA7154E/V2/G NXP Semiconductors, SAA7154E/V2/G Datasheet
SAA7154E/V2/G
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SAA7154E/V2/G Summary of contents
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SAA7154E; SAA7154H Multistandard video decoder with comb filter, component input and RGB output Rev. 02 — 6 December 2007 1. General description The SAA7154E; SAA7154H is a high-quality multistandard video decoder supporting 10-bit Analog-to-Digital Converter (ADC), enhanced PAL/NTSC comb filtering, ...
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... NXP Semiconductors The decoded video (the digitized component video, respectively) can be output on an 8-bit or 10-bit wide ITU-656 expansion port (X-port); alternatively decoded video can be fed to a versatile video scaler to the Image port (I-port), which can be 8-bit, 16-bit or 24-bit wide. An analog On-Screen Display (OSD) interface allows to mix OSD data on the I-port and X-port video data ...
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... NXP Semiconductors I Versatile VBI data decoder, slicer, clock regeneration and byte synchronization N I Gemstar2x, WSS625, WSS525 (CGMS), XDS and V-chip) N Optionally, raw data with dedicated gain and offset adjustment is available for software decoding I On-chip Line-Locked Clock (LLC) generation according to ITU-601 (standard defi ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name SAA7154E/V2/G LBGA156 plastic low profile ball grid array package; 156 balls; body 15 SAA7154H/V2 QFP160 SAA7154E_SAA7154H_2 Product data sheet Description plastic quad flat package; 160 leads (lead length 1.6 mm); ...
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GPIN OSD_FSW 3-BIT FAST SWITCH ADC (3) CONTROL 3-BIT AIxD OSD COMPONENT ADC (3) differential PROCESSING input R G COMPONENT AI11 PROCESSING B ANALOG INPUT VIDEO 16 PROCESSING ADC1 analog to input CROMINANCE ADC4 CVBS lines LUMINANCE Y PROCESSING AI44 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration (LBGA156) Table 2. Pin Symbol Row A A2 XTOUT A6 XRDY A10 XPD4 Row B B1 AI41 B5 TDI B9 XPD3 B13 IXD2 Row SSA4 C5 V DDD13 C9 V DDD11 C13 IXD4 Row D D1 AI43 D5 V SSD13 D9 V SSD11 ...
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... NXP Semiconductors Table 2. Pin Symbol Row E E1 AI44 E11 HPD1 Row F F1 AI3D F11 V Row G G1 AI34 G11 V Row H H1 AI2D H11 IPD2 Row J11 V Row K K1 AI12 K11 IPD7 Row L13 IDQ Row M M1 AOUT1 M13 OSD_FSW Row N N1 AOUT2 ...
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... NXP Semiconductors Fig 4. Pin configuration (QFP160) Table 3. Pin Symbol 1 i.c. 2 AI41 3 AGND 4 V SSA4 5 AI42 6 AI4D 7 AI43 8 V DDA4 9 V DDA4A 10 AI44 11 AI31 12 V SSA3 13 AI32 14 AI3D 15 AI33 16 V DDA3 17 V DDA3A 18 AI34 19 AI21 20 V SSA2 21 AI22 22 AI2D 23 AI23 24 V DDA2 ...
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... NXP Semiconductors Table 3. Pin Symbol 29 AI12 30 AI1D 31 AI13 AI14 35 AGNDA 36 AOUT1 AOUT2 40 V [1] i.c.: internally connected; leave open. n.c.: not connected. 6.2 Pin description Pins sorted by functions. Table 4. Symbol Supplies (analog) AGND AGNDA V DDA0 V DDA1 V DDA1A V DDA2 V DDA2A V DDA3 V DDA3A V DDA4 ...
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... NXP Semiconductors Table 4. Symbol Supplies (digital) V DDD1 V DDD2 V DDD3 V DDD4 V DDD5 V DDD6 V DDD7 V DDD8 V DDD9 V DDD10 V DDD11 V DDD12 V DDD13 V SSD1 V SSD2 V SSD3 V SSD4 V SSD5 V SSD6 V SSD7 V SSD8 V SSD9 V SSD10 V SSD11 V SSD12 V SSD13 Analog inputs (see AI11 AI12 AI13 AI14 AI21 AI22 ...
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... NXP Semiconductors Table 4. Symbol AI34 AI41 AI42 AI43 AI44 AI1D AI2D AI3D AI4D Analog outputs (see AOUT1 AOUT2 Audio clock (see ALRCLK AMCLK ASCLK AMXCLK 2 I C-bus SCL SDA INT_A General control GPIN CE RES_N OSD input (see OSD1 OSD2 OSD3 OSD_FSW 83 ...
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... NXP Semiconductors Table 4. Symbol IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 ICLK IDQ IGP1 IGP0 IGPH IGPV ITRDY ITRI Image I-port 2 (IX-port) IXD7 IXD6 IXD5 IXD4 IXD3 IXD2 IXD1 IXD0 Expansion port (X-port; see XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 ...
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... NXP Semiconductors Table 4. Symbol XRDY XRH XRV XTRI Host port (H-port; see HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 Real-time clock (see RTCO RTS1 RTS0 Clocks (see LLC LLC2_54 XTALI XTALO XTOUT Boundary scan test TCK TDI SAA7154E_SAA7154H_2 Product data sheet Pin description … ...
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... NXP Semiconductors Table 4. Symbol TDO TMS TRST_N Pins not in use i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. [ analog input output power strapping pull-up pull-down open-drain. [2] Pin strapping is done by connecting the pin to the supply through a 4.7 k resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level ...
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... NXP Semiconductors 7. Functional description 7.1 Analog front-end 7.1.1 Features The SAA7154E; SAA7154H offers sixteen analog signal inputs which supply the signals to four analog main channels with source switches, clamp circuits, analog amplifiers and 10-bit CMOS ADCs with decimation filters. The SAA7154E; SAA7154H has some auxiliary inputs which can be utilized to detect 3-level confi ...
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... NXP Semiconductors CONNECTOR CVBS/Y:AI11 R/C:AI21 G:AI31 B:AI41 SCART 1 AV:AI33 FSW:AI34 CVBS:AOUT1 CVBS/Y:AI12 R/C:AI22 G:AI32 B:AI42 SCART 2 AV:AI43 FSW:AI44 CVBS:AOUT2 Y:AI14 Y/C FRONT PANEL C:AI24 CONNECTOR CVBS:AI13 TUNER 1 CVBS:AI23 TUNER 2 OSD-R: AI22 OSD-G: AI32 OSD OSD-B: AI42 IN FSW: AI44 Fig 5. Analog front-end 7.1.1.1 D-terminal and SCART confi ...
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... NXP Semiconductors Fast blanking (RGB switch control): basis either a CVBS or a RGB signal (which is usually menu information or teletext synchronized with CVBS). Since the switch control signal is generally at a different clock rate than the system clock (although both are line-locked), the sampling instance for this signal sometimes might show some uncertainties if a standard bi-level input is used. The SAA7154E ...
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... NXP Semiconductors Decimation filtering is required to remove aliasing artifacts that can result from 4-fold oversampling of SDTV signals (54 MHz sampling frequency and 13.5 MHz pixel rate) and 2-fold oversampling of HDTV signals. AI11 INPUT AI12 SELECTION AI13 4x MUX AI14 AI21 AI22 AI23 AI24 AI31 ...
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CVBS-IN or Y-IN DELAY LDEL COMPARATOR YCOMB CHR UV QUADRATURE MODULATOR CVBS-IN or LOW PASS 1 MIXER CHR-IN DOWN SAMPLING LCBW[2:0] SUBCARRIER GENERATION 2 CHROMINANCE LDEL INCREMENT YCOMB DELAY CHROMINANCE SUBCARRIER INCREMENT GENERATION DTO RESET 1 SUBCARRIER INCREMENT GENERATION HUEC ...
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... NXP Semiconductors 7.2.1 Comb filter operation Super-adaptive separation for: • Increased luminance and chrominance bandwidth for all PAL and NTSC standards • Reduced cross-color and cross-luminance artifacts, even with critical color patterns. The decision logic of the 2-dimensional comb filter in the SAA7154E; SAA7154H is improved in order to reduce residual artifacts (namely cross-color and cross-luminance (dots)) ...
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... NXP Semiconductors To avoid these undesired effects, the recognition of the vertical synchronization pulse has been improved. A reference for the improved synchronization behavior is the selected tape material. The odd/even field detection has been made more robust. The detection signal is low-pass filtered by a field-count programmable flywheel to exclude all noise peaks of weak VCR signals ...
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... NXP Semiconductors The OSD processing (see OSD signal provided by an external device (e.g. teletext decoder SAA5697). Three ADCs (OSD1, OSD2 and OSD3) convert the three analog RGB inputs AI22, AI32 and AI42 into 3-bit digital streams. The corresponding FSW signal is also converted from the analog input AI44 to a 3-bit digital signal by the separate ADC OSD4 ...
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... NXP Semiconductors Blue stretching: sufficient contrast towards more blue to obtain a brighter impression of the picture. The blue stretch gravity block works slightly different to the gravity block described above. The center of gravity here is not the same as the center of the programmable range. The center of range is fi ...
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... NXP Semiconductors Fig 10. Center frequencies of luminance sharpness control 7.6.1.4 Histogram collection The histogram collection provides the following features: • Histogram adaption by means of three programmable Look-Up Tables (LUT) for: – Adaptive black stretch – White stretch – Dynamic Contrast Improvement (DCI) • ...
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... NXP Semiconductors 7.6.2 Scaler The high-performance video scaler offers non-linear horizontal scaling, thus enabling e.g. optimized zooming sources display (panorama scaling). An intrafield de-interlacer (no external memory needed) converts interlaced sources to progressive format, suitable for direct display on LCD panels. An on-chip display and raster generator enables direct driving of LCD panels ...
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... NXP Semiconductors Fig 12. Functional block diagram of the scaler data path The input/output data relation limits overall H and V zooming. The video scaler receives its input signal from the video decoder or from the expansion port (X-port). It gets 16-bit Y-C 27 MHz from the decoder. A discontinuous data stream can be accepted from the expansion port (X-port), normally 8-bit wide ITU-656 like Y-C pixel qualifi ...
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... NXP Semiconductors Each programming page contains control for: • Signal source selection and formats • Task handling and trigger conditions • Input and output acquisition window definition • H-prescaler, V-scaler and H-phase scaling. Raw VBI data is handled as specific input format and needs its own programming page (equals own task) ...
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... NXP Semiconductors separate bytes (where the hardware sets the upper bits to 00b). For transfer over I-port the result is buffered into a dedicated VBI data FIFO with a capacity double words). The programming registers 40h to 5Fh control the VBI data slicing and data transfer. ...
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... NXP Semiconductors Table 6. Data type Data types for SDTV input (subaddress 48h/4Ah address 09h control bit SEL_HD = 0b 7.8 Image port output interface The output interface consists of an output formatter, a FIFO for video and for sliced text data, an arbitration circuit which controls the mixed transfer of video and sliced text data over the I-port and a decoding and multiplexing unit which generates the 8-bit or 16-bit wide output data stream and the accompanied reference and supporting information ...
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... NXP Semiconductors The data stream at the scaler output is accompanied by a data valid flag (or data qualifier). The discontinuous output data after the scaling process can be output as they occur or the data may be packed to continuous output lines by means of a trigger mechanism, which is controlled by a separate sync generator. ...
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... NXP Semiconductors The exception to the above is the VBI interrupt bit whose status is frozen when a VBI event occurs set only if its mask bit is set and an end of VBI event occurs. An additional interrupt lost signal is available for software to check whether all VBI data has been read ...
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... NXP Semiconductors An other option is to use the second CGC for jitter removal from the frame-locked audio clock generated inside the SAA7154E; SAA7154H. Supported audio clock frequencies of the low jitter frame locked audio clock from the audio master clock are (with f • ...
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... NXP Semiconductors XTALO LLC2_54 RES_N Fig 13. Timing diagram of reset sequence 7.13.2 Initial programming sequence after power-on After power-on a sequence of register changes needs to be performed, due to internal dependencies on the clock generation: 1. The first programming of the device needs to be done with slave address 42h/40h, bits XPE[1:0] = 01b 2 ...
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... NXP Semiconductors 7.14.1 Analog terminals The SAA7154E; SAA7154H has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite video CVBS or s-video Y/C signal pairs or component video input signals RGB plus separate sync (or Y-P Component signals with e.g. sync-on-Y or sync-on-green are also supported; they are fed to two ADC channels, one for the video content, the other for sync conversion ...
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... NXP Semiconductors Table 9. Pin AMCLK AMXCLK I ASCLK ALRCLK [1] See 7.14.3 Clock and real-time synchronization signals at the RT-port The generation of the line-locked video clock LLC (pixel clock) and of the frame-locked audio serial bit clock requires a crystal accurate frequency reference. An oscillator is built-in for fundamental or third harmonic crystals (the SAA7154E; SAA7154H supports crystals with 32 ...
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... NXP Semiconductors Table 10. Pin RTCO RTS0 RTS1 [1] See 7.14.4 Video expansion port through the X-port 7.14.4.1 General The expansion port (X-port) can be used either to output 8-bit or 10-bit video from the comb filter decoder or component path directly or to receive video data from other external digital video sources such as a MPEG decoder for output at the image port (I-port). The X-port output is only capable of delivering SDTV signals ...
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... NXP Semiconductors Table 11. Pin XPD7 to XPD0 HPD7 to HPD0 XCLK XDQ XRDY XRH XRV XTRI 7.14.4.2 Timing Table 12. Control signal HREF F_ITU656 V123 VGATE FID HS CREF2 CREF SAA7154E_SAA7154H_2 Product data sheet Signals dedicated to the expansion port I/O Description I/O X-port data: in output mode controlled by decoder section ...
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... NXP Semiconductors ITU counting 622 623 310 single field counting 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID ITU counting 309 310 single field counting 310 309 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134h VGATE FID (1) The signal HREF at the negative edge of signal V123 indicates whether this field is odd or even. If HREF is logic 1, the field is odd (fi ...
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... NXP Semiconductors ITU counting 525 single field counting 262 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID ITU counting 263 262 single field counting 262 263 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101h VGATE FID (1) The signal HREF at the negative edge of signal V123 indicates whether this field is odd or even. If HREF is logic 1, the field is odd (fi ...
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... NXP Semiconductors Fig 16. Horizontal timing diagram (50 Hz/60 Hz) 7.14.4.3 X-port configured as output If data output is enabled at the expansion port, then the data stream from the decoder is presented. The data format of the 8-bit/10-bit data bus is dependent on the chosen data type, selectable by the line control registers LCR2 to LCR24. In contrast to the image port, the sliced data format is not available on the expansion port ...
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... NXP Semiconductors 7.14.4.4 X-port configured as input If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder or from the expansion port (controlled by bits SCSRC[1:0]). Byte serial or 16-bit wide Y-C schemes or raw samples from an external ADC may be input (bits FSC[2:0]; see Table 17), where the H-port serves as the port for the chrominance input path ...
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... NXP Semiconductors Table 13. Pin IPD7 to IPD0 HPD7 to HPD0 IXD7 to IXD0 ICLK IDQ IGPH IGPV IGP1 IGP0 ITRDY ITRI [1] See 7.14.5.2 Digital OSD It is possible to insert OSD-information into the I-port video signal. This can be done with an external OSD controller, which is connected to the IPORT clock (ICLK), the I-port sync signals (IGPH and IGPV) and the OSD control pins (OSD[3:0]) ...
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... NXP Semiconductors 2 7.15 I C-bus registers 7.15.1 Register overview of basic functions Access the registers from Table 15. Address 00h 01h to 1Fh 20h to 2Fh 30h to 3Fh 40h to 7Fh X-port, I-port and scaler 8h0 to 8Fh 9h0 to BFh C0h to EFh SAA7154E_SAA7154H_2 Product data sheet Table 15 through the slave write address 42h/40h. ...
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Table 16. Register 00h used by chip version part Basic register function Subaddress D7 [1] Chip version 00h [1] Read only. Table 17. Registers 01h to 1Fh used by the video decoder part Basic register function Subaddress D7 Increment delay ...
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Table 17. Registers 01h to 1Fh used by the video decoder part Basic register function Subaddress D7 Raw data gain 18h Raw data offset 19h Color killer 1Ah MISC and TVVCRDET 1Bh Enhanced comb control 1 1Ch MISC and enhanced ...
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Table 19. Registers 30h to 3Fh used by audio clock generator Basic register function Subaddress D7 Audio master clock cycles per field 30h Audio master clock cycles per field 31h Audio master clock cycles per field 32h [1] Reserved 33h ...
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Table 20. Registers 40h to 7Fh used by general purpose VBI data slicer Basic register function Subaddress D7 HOFF 59h VOFF 5Ah HVOFF 5Bh [1] Reserved 5Ch Sliced data output mode 5Dh Sliced data 5Eh GS2 capture control 5Fh Line ...
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Table 20. Registers 40h to 7Fh used by general purpose VBI data slicer Basic register function Subaddress C-bus read-back 19 GS2-data byte 1 78h 2 I C-bus read-back 20 GS2-data byte 2 79h 2 I C-bus read-back ...
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Table 22. Registers 90h to BFh used for task A definition Basic register function Subaddress D7 Basic settings and acquisition window definition Task handling control 90h X-port formats and configuration 91h X-port Input reference signal 92h definition I-port formats and ...
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Table 22. Registers 90h to BFh used for task A definition Basic register function Subaddress D7 Horizontal phase offset luminance AAh [1] Reserved ABh Horizontal scaling increment ACh chrominance ADh Horizontal phase offset chrominance AEh [1] Reserved AFh Vertical scaling ...
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Table 23. Registers C0h to EFh used for task B definition Basic register function Subaddress D7 Basic settings and acquisition window definition Task handling control C0h X-port formats and configuration C1h Input reference signal definition C2h control I-port formats and ...
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Table 23. Registers C0h to EFh used for task B definition Basic register function Subaddress D7 Horizontal phase offset luminance DAh [1] Reserved DBh Horizontal scaling increment DCh chrominance DDh Horizontal phase offset chrominance DEh [1] Reserved DFh Vertical scaling ...
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... NXP Semiconductors 7.15.2 Register overview extended functions Access the registers from Table 24. Address 00h to 1Fh 20h to 3Fh 40h to 4Fh 50h to 59h 60h to 78h 80h to 8Bh 8Ch to BFh C0h to CFh D0h to DFh E0h to FFh SAA7154E_SAA7154H_2 Product data sheet Table 24 through the slave write address 4Ah/48h. ...
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Table 25. Register 00h to 1Fh used by HDTV-synchronization Extended register function Subaddress D7 [1] Reserved 00h [1] Reserved 01h MSB horizontal reference stop/start 02h Horizontal reference stop 03h Horizontal reference start 04h MSB horizontal sync start/stop 05h Horizontal sync ...
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Table 26. Registers 20h to 3Fh used by Analog Input Control (AIC) expert mode and extended analog input/output functions Extended register function Subaddress D7 Target values digital clamping 1, 2 26h Target values digital clamping 2, 3 27h Target values ...
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Table 27. Registers 40h to 4Fh used by Analog Input Control (AIC) expert mode status (read only) Extended register function Subaddress D7 Unused lower range of previous field 40h Unused lower range of previous field, 41h Unused upper range of ...
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Table 28. Registers 50h to 59h used by color improvement (gravity functions) Extended register function Subaddress D7 Gravity 32 57h Gravity 33 58h Gravity 4 59h [1] Reserved 5Ah to 5Fh [1] Do not change these values. Table 29. Registers ...
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Table 29. Registers 60h to 78h used by OSD …continued Extended register function Subaddress D7 FSW OSD control 2 75h FSW OSD control 3 76h Overlay OSD control 77h Comp. OSD dither, peaking, delay 78h [1] Reserved 79h to 7Fh ...
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Table 31. Registers 8Ch to BFh used by scaler post processing look-up tables Extended register function Subaddress D7 [1] Reserved 8Fh Green path 90h 91h 92h to 9Dh 9Eh 9Fh Blue path A0h A1h A2h to ADh AEh AFh Red ...
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Table 32. Registers C0h to CFh used by histogram collection Extended register function Subaddress D7 Histogram control 4 C4h Histogram control 5 C5h Histogram control 6 C6h Histogram control 7 C7h [1] Reserved C8h to CFh [1] Do not change ...
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Table 34. Registers E0h to FFh used by second PLL/CG (PLL2/CG2) and raster generator Extended register function Subaddress D7 LFCOs per line E0h P-/I-parameter select, PLL mode, E1h PLL H-Source, LFCOs per line Nominal PLL2 DTO increment E2h E3h S_PLL ...
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Table 34. Registers E0h to FFh used by second PLL/CG (PLL2/CG2) and raster generator Extended register function Subaddress D7 HActive begin FAh HActive begin/stop FBh HActive stop FCh VGate begin FDh VGate begin/stop FEh VGate stop FFh …continued D6 D5 ...
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... NXP Semiconductors 8. Limiting values Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Analog supply voltage V analog supply voltage 1 DDA1 V analog supply voltage 1A DDA1A V analog supply voltage 2 DDA2 V analog supply voltage 2A DDA2A V analog supply voltage 3 DDA3 ...
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... Thermal characteristics Parameter thermal resistance from junction to ambient in free air SAA7154E/V2/G SAA7154H/V2 value can vary depending on the board layout. To minimize the effective R th(j- 3.6 V; core V DDD DDD = 1. 1. ...
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... NXP Semiconductors Table 37. Supplies …continued Symbol Parameter V crystal analog supply voltage DDA(XTAL) V analog supply voltage (1.8 V) DDA_A18 V analog supply voltage (1.8 V) DDA_C18 Digital core supply voltage V digital supply voltage 2 DDD2 V digital supply voltage 4 DDD4 V digital supply voltage 7 DDD7 V digital supply voltage 8 ...
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... NXP Semiconductors Table 38. Analog part …continued Symbol Parameter Z input impedance i C input capacitance i channel crosstalk ct(ch) V peak-to-peak output voltage on pin AOUT1 or AOUT2; for normal video levels o(p-p) B bandwidth 10-bit ADC (including analog clamp and gain stages) B bandwidth differential phase dif G differential gain ...
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... NXP Semiconductors Table 40. Clocks and oscillators Symbol Parameter Clock output timing (pins LLC and LLC2_54) C output load capacitance o(L) T cycle time cy duty cycle t rise time r t fall time f t delay time from LLC to d(LLC-LLC2_54) LLC2_54 Horizontal PLL f nominal line frequency nom(line) ...
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... NXP Semiconductors Table 40. Clocks and oscillators Symbol Parameter Crystal specification (X1) T ambient temperature amb C load capacitance L R resonant series resistor s(rsn) C motional capacitance 1 C shunt capacitance 0 [1] The effects of rise and fall times are included in the calculation of t illustrated in Figure 17 ...
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... NXP Semiconductors Table 41. X-port …continued Attention: Digital inputs and I/O ports are not 5 V tolerant. Symbol Parameter Data and control signal output timing X-port, related to XCLK output t data output hold time h(Q) t propagation delay PD [1] From internal PLL (clock oscillator) [2] The effects of rise and fall times are included in the calculation of t ...
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... NXP Semiconductors clock output LLC clock output LLC2_54 Fig 17. Line-Locked Clock (LLC) output timing clock output XCLK data and control inputs (X port) data and control outputs X port (1) See (2) See Fig 18. X-port input and output timing SAA7154E_SAA7154H_2 Product data sheet t LLCH t d(LLC ...
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... NXP Semiconductors clock input or output ICLK data and control outputs I port (1) See Fig 19. I-port, IX-port and H-port output timing 11. Application information 11.1 General schematics The schematics from all analog inputs can be used either as CVBS or Y/C inputs. For best performance all analog inputs intended for RGB or YUV components only should be terminated directly by ...
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... NXP Semiconductors SYNC(CVBS)/Y Fig 21. Connection for RGB with SYNC on separate input SAA7154E_SAA7154H_2 Product data sheet SAA7154E; SAA7154H Multistandard video decoder with comb filter for input levels R/C AIx2 AIx4 AIx3 AIx1 SYNC(CVBS)/Y 47 Rev. 02 — 6 December 2007 for input levels 4 dB ...
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... NXP Semiconductors 11.2 Oscillator applications SAA7154 B4 (155) A3 (156) XTALI XTALO 32.11 MHz 4 001aab954 a. With 3rd harmonic quartz crystal. Crystal load pF. L SAA7154 B4 (155) A3 (156) XTALI XTALO 24.576 MHz 4 001aab960 d. With 3rd harmonic quartz crystal. Crystal load pF. L SAA7154 B4 (155) A3 (156) XTALI XTALO 32 ...
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... NXP Semiconductors 11.3 3-bit ADC application The SAA7154E; SAA7154H has 3-bit ADCs, which can be selected on input groups AI3x and AI4x. They permit many applications (see Section • DC-level detection for D-connector and SCART • FSW-control • external VGA vertical sync input • ...
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... NXP Semiconductors 11.4 Digital OSD application Figure 24 MTV048. Fig 24. Application of SAA7154E; SAA7154H and an OSD controller chip (e.g. Myson 12. Test information 12.1 Boundary scan test The SAA7154E; SAA7154H has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware. The SAA7154E; ...
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... NXP Semiconductors Table 45. Instruction SAMPLE CLAMP IDCODE 12.1.1 Initialization of boundary scan circuit The Test Access Port (TAP) controller should be in the reset state (TEST_LOGIC_RESET) when the functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. ...
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... NXP Semiconductors 13. Package outline LBGA156: plastic low profile ball grid array package; 156 balls; body 1.05 mm ball A1 index area ball index area 2 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.45 1.20 0.55 mm 1.65 0.35 0.95 0.45 OUTLINE VERSION IEC SOT700 Fig 26. Package outline SOT700-1 (LBGA156) ...
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... NXP Semiconductors QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 3.4 mm; high stand-off height y 120 121 pin 1 index 160 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.50 3.6 mm 4.07 0.25 0.25 3.2 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 48. Acronym ACM ADC AGC AIC ANC AV BCS BST CC CCST CE CG CGC CGMS ...
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... NXP Semiconductors Table 48. Acronym DVD EAV EDGI ESD FIFO FIR FSW HDTV 2 I C-bus I/O ISD ITU JEDEC JTAG LCD LLC LSB LUT MOS MPEG MSB MUX NABTS NTSC OSD PAL PC PLL PVR RGB RMS RTC RTCO SAV SCART SECAM SDTV ...
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... NXP Semiconductors Table 48. Acronym TFT TTL TV VBI VCR VGA VITC VPD VPS VTR WSS WST XDS XTAL [1] For example, VBI data can be inserted as ANC data into the video stream. [2] X became a synonym for Crys. 16. Glossary H-port — Digital host-port for extension of the image port or expansion port from 8-bit to 16-bit. I-port — ...
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... NXP Semiconductors 17. Revision history Table 49. Revision history Document ID Release date SAA7154E_SAA7154H_2 20071206 • Modifications: Update of active types (see • Adding limiting values for latch-up currents (see • Update of ESD related documents (see • Presenting information more clearly (see • Adding missing abbreviations • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18.5 Patents Notice is herewith given that the subject device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions. US 4,907,093 — owned by Macrovision Corporation. 19. Contact information For additional information, please visit: For sales office addresses, send an email to: ...
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... NXP Semiconductors 20. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin allocation table LBGA156 package Table 3. Pin allocation table QFP160 package Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 5. 60 Hz/525 lines VBI data types supported by the data slicer block . . . . . . . . . . . . . . . . . . . . .28 Table 6. 50 Hz/625 Lines VBI data types supported by the data slicer block ...
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... NXP Semiconductors 21. Figures Fig 1. System block diagram . . . . . . . . . . . . . . . . . . . . . .1 Fig 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. Pin configuration (LBGA156 Fig 4. Pin configuration (QFP160 Fig 5. Analog front-end . . . . . . . . . . . . . . . . . . . . . . . . .16 Fig 6. Analog video inputs and analog input control . . .18 Fig 7. Chrominance and luminance processing, adaptive comb filter . . . . . . . . . . . . . . . . . . . . . . .19 Fig 8. Functional overview of OSD . . . . . . . . . . . . . . . .21 Fig 9. Simplifi ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Improvements over SAA7119 . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 15 7.1 Analog front-end . . . . . . . . . . . . . . . . . . . . . . . 15 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1.1.1 D-terminal and SCART configuration . . . . . . . 16 7 ...
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... NXP Semiconductors 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SAA7154E; SAA7154H Multistandard video decoder with comb filter Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...