SAA7154E/V2/G NXP Semiconductors, SAA7154E/V2/G Datasheet - Page 30

• Manufacturer Part Number: SAA7154E/V2/G
• Manufacturer: NXP Semiconductors

Specifications of SAA7154E/V2/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
7.10 Interrupt control
7.9 Digital OSD
The data stream at the scaler output is accompanied by a data valid flag (or data
qualifier).
The discontinuous output data after the scaling process can be output as they occur or the
data may be packed to continuous output lines by means of a trigger mechanism, which is
controlled by a separate sync generator.
Clock cycles with invalid data on the I-port data bus (including pins HPD[7:0] in 16-bit
output mode) can be handled in two different ways (controlled by bit INS80). As before,
invalid cycles may be marked with 00h, but additionally a blanking value insertion (80h
and 10h) is implemented as required by ITU-656 .
The output interface also arbitrates the transfer between scaled video data and sliced text
data over the I-port output. The bits SLDOM and VITX control the arbitration.
As a further operation the serialization of the internal double pixel double words to 8-bit,
16-bit or 24-bit output, as well as the insertion of the extended ITU-656 codes (SAV/EAV
for video data, ANC or SAV/EAV codes for sliced text data) are done here. Setting bit
ICODE = 1b activates the leading/trailing sequences. For 16-bit and 24-bit output modes
(bits ICKS[3:2] = 00b) the leading/trailing sequences occur on each 8-bit wide port as a
serial byte pattern.
When any valid input signal is missing, a blue screen signal can be inserted under
software control in order to get a valid output signal. I
horizontal or vertical lock.
The SAA7154E; SAA7154H can perform overlay of On-Screen-Display (OSD) information
in display (panel) raster timing by using the digital OSD function. For the digital OSD
function, a separate combined input port (3-bit data, 1-bit switch control) is available
behind the scaler, programmable color mapping of the data bits is provided. Appropriate
OSD controllers can insert menu overlay and the like, unaffected of any scaling ratio, thus
providing optimum readability.
When any valid input signal is missing, a blue screen signal can be inserted under
software control in order to get a valid RGB output signal. I
criteria like horizontal or vertical lock. The SAA7154E; SAA7154H can perform overlay of
On-Screen-Display (OSD) information for RGB output signals on I-port. The OSD
information runs in display panel raster timing. For an application example
The SAA7154E; SAA7154H is able to generate an interrupt (pin INT_A, open-drain, active
LOW) from up to 16 important internal status signals (see
status signals for the interrupt generation must be enabled by writing the interrupt mask
registers at 2Dh to 2Fh from the first I
always enabled. By default all interrupts are disabled (except PRDON). An interrupt will be
deasserted once the status register containing the corresponding status bit is read.
The status information read after an interrupt will always be the latest state, therefore the
status is not frozen when an interrupt is generated. If there is a delay in reading an
interrupt status, the interrupt condition may be superseded by the next other one.
Rev. 02 — 6 December 2007
2
C-bus slave address, except PRDON, which is
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
2
C-bus status bits provide criteria like
Table
2
C-bus status bits provide
7). The usage of these
© NXP B.V. 2007. All rights reserved.
Figure
24.
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