SAF7118HV1 NXP Semiconductors, SAF7118HV1 Datasheet - Page 63

• Manufacturer Part Number: SAF7118HV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118HV1

• Screening Level: Industrial
• Package Type: PQFP
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF7118_4
Product data sheet
8.6.3 Text FIFO
8.6.4 Video and text arbitration (subaddress 86h)
These are:
The trigger levels for FAE and FAF are programmable by FFL[1:0] 86h[3:2] (16, 24, 28,
full) and FEL[1:0] 86h[1:0] (16, 8, 4, empty).
The state of this flag can be seen on pins IGP0 or IGP1. The pin mapping is defined by
subaddresses 84h and 85h; see
The data of the internal VBI data slicer is collected in the text FIFO before the
transmission over the I port is requested (normally before the video window starts). It is
partitioned into two FIFO sections. A complete line is filled into the FIFO before a data
transfer is requested. So normally, one line of text data is ready for transfer, while the next
text line is collected. Thus sliced text data is delivered as a block of qualified data, without
any qualification gaps in the byte stream of the I port.
The decoded VBI data is collected in the dedicated VBI data FIFO. After the capture of a
line has been completed, the FIFO can be streamed through the image port, preceded by
a header, giving line number and standard.
The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The
decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5Dh[5:0] at value
< 3Eh) or by SAV/EAV codes selectable by DID[5:0] at value 3Eh or 3Fh. Pin IGP0 or
IGP1 is set if the first byte of the ANC header is valid on the I port bus. It is reset if an SAV
occurs. So it may frame multiple lines of text data output, in the event that the video
processing starts with a distance of several video lines to the region of text data. Valid
sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is
set and the data qualifier is active on pin IDQ.
The decoded VBI data is presented in two different data formats, controlled by bit
RECODE.
Sliced text data and scaled video data are transferred over the same bus, the I port. The
mixed transfer is controlled by an arbitration circuit.
If the video data is transferred without any interrupt and the video FIFO does not need to
buffer any output pixel, the text data is inserted after the end of a scaled video line,
normally during the blanking interval of the video.
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The FIFO Almost Empty (FAE) flag
The FIFO Combined Flag (FCF) or FIFO filled, which is set at almost full level and
reset, with hysteresis, only after the level crosses below the almost empty mark
The FIFO Almost Full (FAF) flag
The FIFO Overflow (FOVL) flag
RECODE = 1: values 00h and FFh will be recoded to even parity values 03h and FCh
RECODE = 0: values 00h and FFh may occur in the data stream as detected
Rev. 04 — 4 July 2008
Multistandard video decoder with adaptive comb filter
Section
9.6.
SAF7118
© NXP B.V. 2008. All rights reserved.
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