SAF7118HV1 NXP Semiconductors, SAF7118HV1 Datasheet - Page 78

• Manufacturer Part Number: SAF7118HV1
• Manufacturer: NXP Semiconductors

Specifications of SAF7118HV1

• Screening Level: Industrial
• Package Type: PQFP
• Pin Count: 160
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF7118_4
Product data sheet
9.7 Host port for 16-bit extension of video data I/O (H port)
There are no empty cycles in the ancillary code and its data field. The data codes 00h
and FFh are suppressed (changed to 01h or FEh respectively) in the active video stream,
as well as in the VBI raw sample stream (VBI pass-through). Optionally, the number range
can be further limited.
Table 33.
[1]
The H port pins HPD can be used for extension of the data I/O paths to 16-bit.
The I port has functional priority. If I8_16[93h[6]] is set to logic 1 the output drivers of the
H port are enabled depending on the I port enable control. For I8_16 = 0, the HPD output
is disabled.
Symbol Pin
IPD7 to
IPD0
ICLK
IDQ
IGPH
IGPV
IGP1
IGP0
ITRDY
ITRI
– Recoded VBI data bytes (8-bit) directly placed in ANC data field, 00h and FFh
Pin numbers for QFP160 in parenthesis.
codes will be recoded to even parity codes 03h and FCh to suppress invalid
ITU-R BT.656 codes
K11, J13,
J14, H13,
H14, H11,
G12 and G14
(92 to 94, 97
to 100 and
102)
M14 (84)
L13 (85)
K12 (91)
K14 (90)
K13 (89)
L14 (87)
N12 (77)
L12 (86)
Signals dedicated to the image port
[1]
I/O
I/O
I/O
O
O
O
O
O
I
I
Rev. 04 — 4 July 2008
Description
I port data
continuous reference clock at image port,
can be input or output, as output decoder
LLC or XCLK from X port
data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock
horizontal reference output signal, copy of
the H gate signal of the scaler, with
programmable polarity; alternative function:
HRESET pulse
vertical reference output signal, copy of the
V gate signal of the scaler, with
programmable polarity; alternative function:
VRESET pulse
general purpose output signal for I port
general purpose output signal for I port
target ready input signals
port control, switches I port into 3-state
Multistandard video decoder with adaptive comb filter
Bit
ICODE[93h[7]],
ISWP[1:0] 85h[7:6]
and
IPE[1:0] 87h[1:0]
ICKS[1:0] 80h[1:0]
and
IPE[1:0] 87h[1:0]
ICKS2[80h[2]],
IDQP[85h[0]] and
IPE[1:0] 87h[1:0]
IDH[1:0] 84h[1:0],
IRHP[85h[1]] and
IPE[1:0] 87h[1:0]
IDV[1:0] 84h[3:2],
IRVP[85h[2]] and
IPE[1:0] 87h[1:0]
IDG12[86h[4]],
IDG1[1:0] 84h[5:4],
IG1P[85h[3]] and
IPE[1:0] 87h[1:0]
IDG02[86h[5]],
IDG0[1:0] 84h[7:6],
IG0P[85h[4]] and
IPE[1:0] 87h[1:0]
-
IPE[1:0] 87h[1:0]
SAF7118
© NXP B.V. 2008. All rights reserved.
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