935274109557 NXP Semiconductors, 935274109557 Datasheet - Page 42

935274109557

Manufacturer Part Number
935274109557
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 935274109557

Screening Level
Commercial
Package Type
SQFP
Pin Count
208
Lead Free Status / RoHS Status
Compliant
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Table 17 I
ADR
HEX
40
41
42
43
44
I
I
I
I
I
2
M
C-bus video front-end input interface static settings
625/525
subsampling type R/W 1 byte
video sync format R/W 1 byte
video clock select R/W 1 byte
vertical sync
timing adjustment
COMMAND
NAME
R/W
R/W 1 byte
R/W 2 bytes
SIZE/POSITION
bit[1:0] = 00
bit[1:0] = 01
bit[1:0] = 00
bit[1:0] = 01
bit[1:0] = 10
bit[1:0] = 11
bit[1:0] = 00
bit[1:0] = 01
bit[1:0] = 10
bit 0 = 0
bit 0 = 1
byte 0
byte 1
625
525
D1
2
1
SIF
H-sync, V-sync and Field
Identification (FID)
information coded in the
EAV/SAV bytes complying
to ITU-R BT.656
separate H-sync, V-sync
and FID signals input to
from external source(s)
separate H-sync and
V-sync signals input to
from external source(s)
video clock 1
video clock 2
0 to 225
0 to 225
/
/
3
2
PARAMETER/RANGE
D1
D1
625
D1
0
video clock 1
0, 0
DEFAULT
defines the input signal either as 625 lines
or 525 lines
specifies the subsampling type; remark: if
the subsampling type is changed, then the
horizontal shift (address 45H) will be
overwritten with the default values and the
horizontal filter (addresses 53H, 54H and
55H) will be initialized with appropriate
parameter
defines the incoming video sync sources
defines which external video input clock is
used
Remark: If a vertical sync timing
adjustment different from ‘0’ is used, then
a horizontal shift of minimum 2 pixels must
be programmed in subaddress 45H.
defines the number of shifted lines in the
top field
defines the number of shifted lines in the
bottom field
DESCRIPTION

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