TDA8501T NXP Semiconductors, TDA8501T Datasheet - Page 5

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TDA8501T

Manufacturer Part Number
TDA8501T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TDA8501T

Lead Free Status / RoHS Status
Not Compliant

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Notes
1. Pin 4: in PAL mode, if not connected to external H2 pulse, this pin is the output for the internally generated H/2 signal.
2. The listed voltages connected to pin 17 (if V
April 1993
PAL/NTSC and
Y/Y
NOTCH
Y +SYNC OUT
Y +SYNC IN
BURST ADJ
Y +SYNC OUT
OSC
CS
PAL/NTSC encoder
Pin 4: in NTSC mode, for internal set-up this pin is connected to ground; when internal set-up is switched off, this pin
is connected to V
0 V = PAL mode; at pin 5, Y without sync and input blanking on
5 V = NTSC mode; at pin 5, Y without sync and input blanking on
1.8 V = PAL mode; at pin 5, Y with sync and input blanking off
3.2 V = NTSC mode; at pin 5, Y with sync and input blanking off
SYMBOL
SYNC
PIN
CC
17
18
19
20
21
22
23
24
.
four level control pin (note 2)
Y +SYNC output via an internal resistor of 2 k ; a notch filter can be connected to this pin
2 V (p-p) nominal Y +SYNC output
Y +SYNC input; (from pin 22) connected to the output of the external delay line
burst current adjustment via external resistor
Y +SYNC output 1 V (p-p) nominal, connected to the input of the external delay line
oscillator tuning: connected to either a crystal in series with capacitor to ground, or to an
external frequency source via a resistor in series with a capacitor
composite sync input, 0.3 V (p-p) nominal
CC
= + 5 V) enable the following Y (via pin 5) input signal states:
5
DESCRIPTION
Preliminary specification
TDA8501

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