ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 143

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

25. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Microprocessor access to the host controller or the
Fig 11. Access to internal control registers . . . . . . . . . . .21
Fig 12. PIO register access . . . . . . . . . . . . . . . . . . . . . . .21
Fig 13. PIO access for a 16-bit or 32-bit register . . . . . . .22
Fig 14. HC and OTG interrupt logic . . . . . . . . . . . . . . . . .27
Fig 15. Internal power-on reset timing . . . . . . . . . . . . . . .30
Fig 16. Clock with respect to the external power-on
Fig 17. HNP sequence of events . . . . . . . . . . . . . . . . . . .33
Fig 18. Dual-role A-device state diagram. . . . . . . . . . . . .35
Fig 19. Dual-role B-device state diagram. . . . . . . . . . . . .36
Fig 20. External capacitors connection . . . . . . . . . . . . . .38
Fig 21. USB host controller states of the ISP1362. . . . . .39
Fig 22. PTD data stored in the buffer memory . . . . . . . . .41
Fig 23. Using internal overcurrent detection circuit . . . . .46
Fig 24. Using external overcurrent detection circuit. . . . .47
Fig 25. Using internal charge pump . . . . . . . . . . . . . . . . .48
Fig 26. Peripheral controller in 8327 compatible DMA
Fig 27. Suspend and resume timing . . . . . . . . . . . . . . . .58
Fig 28. Efficiency as a function of load current . . . . . . .126
Fig 29. Output voltage as a function of load current . . .126
Fig 30. Host controller programmed interface timing . . .129
Fig 31. Peripheral controller programmed interface read
Fig 32. Peripheral controller programmed interface write
Fig 33. Host controller single-cycle DMA timing . . . . . .132
Fig 34. Host controller burst mode DMA timing . . . . . . .133
Fig 35. Peripheral controller single-cycle DMA timing (8237
Fig 36. Peripheral controller single-cycle DMA read timing
Fig 37. Peripheral controller single-cycle DMA write timing
Fig 38. Peripheral controller burst mode DMA timing . .135
Fig 39. Package outline SOT314-2 (LQFP64) . . . . . . . .136
Fig 40. Package outline SOT543-1 (TFBGA64) . . . . . .137
ISP1362_7
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin configuration LQFP64 . . . . . . . . . . . . . . . . . . .6
Pin configuration TFBGA64 . . . . . . . . . . . . . . . . . .6
Recommended values of the ISP1362 buffer
memory allocation . . . . . . . . . . . . . . . . . . . . . . . .15
A sample snapshot of the ATL or INTL memory
management scheme . . . . . . . . . . . . . . . . . . . . .16
A sample snapshot of the ISTL memory
management scheme . . . . . . . . . . . . . . . . . . . . .17
Peripheral controller buffer memory organization 18
PIO interface between a microprocessor and the
ISP1362 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DMA interface between a microprocessor and the
ISP1362 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
peripheral controller . . . . . . . . . . . . . . . . . . . . . . .20
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
timing (I/O and 8237 compatible DMA) . . . . . . .130
timing (I/O and 8237 compatible DMA) . . . . . . .131
mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
in DACK-only mode . . . . . . . . . . . . . . . . . . . . . .134
in DACK-only mode . . . . . . . . . . . . . . . . . . . . . .134
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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