ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 20
ISP1362BDTM
Manufacturer Part Number
ISP1362BDTM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1362BDTM.pdf
(147 pages)
Specifications of ISP1362BDTM
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362BDTM
Manufacturer:
NANYA
Quantity:
1 001
- Current page: 20 of 147
- Download datasheet (5Mb)
ISP1362_7
Product data sheet
8.4 PIO access to internal control registers
Table 5
decoding must combine with the chip select signal (CS) and address lines (A1 and A0).
The direction of access of I/O ports, however, is controlled by the RD and WR signals.
When RD is LOW, the microprocessor reads data from the data port of the ISP1362 (see
Figure
or writes data to the data port (see
Table 5.
The register structure in the ISP1362 is a command-data register pair structure. A
complete register access needs a command phase followed by a data phase. The
command (also named as the index of a register) is used to inform the ISP1362 about the
register that will be accessed at the data phase.
On the 16-bit data bus of a microprocessor, a command occupies the lower byte and the
upper byte is filled with zeros (see
For 32-bit registers, the access cycle is shown in
phase followed by two data phases.
CS
LOW
LOW
LOW
LOW
Fig 10. Microprocessor access to the host controller or the peripheral controller
10). When WR is LOW, the microprocessor writes command to the command port
shows the I/O port addressing in the ISP1362. The complete I/O port address
When A1 = LOW, the microprocessor accesses the host controller.
When A1 = HIGH, the microprocessor accesses the peripheral controller.
A1
LOW
LOW
HIGH
HIGH
I/O port addressing
A0
LOW
HIGH
LOW
HIGH
Rev. 07 — 29 September 2009
microprocessor
Access
R/W
W
R/W
W
bus interface
A1
Figure
Figure
16 bits
Data bus width
16 bits
16 bits
16 bits
Bus interface
12).
11).
0
1
Device bus interface
Host bus interface
Figure
host controller data port
host controller command port
peripheral controller data port
peripheral controller command port
004aaa122
Description
Single-chip USB OTG controller
13. It consists of a command
© ST-ERICSSON 2009. All rights reserved.
ISP1362
20 of 147
Related parts for ISP1362BDTM
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet: