ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 58
ISP1362BDTM
Manufacturer Part Number
ISP1362BDTM
Description
Manufacturer
STEricsson
Datasheet
1.ISP1362BDTM.pdf
(147 pages)
Specifications of ISP1362BDTM
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362BDTM
Manufacturer:
NANYA
Quantity:
1 001
- Current page: 58 of 147
- Download datasheet (5Mb)
ISP1362_7
Product data sheet
Fig 27. Suspend and resume timing
D_SUSPEND/D_WAKEUP
GOSUSP (bit)
USB bus
INT2
CS
The peripheral controller in the ISP1362 will remain in the suspend state for at least 5 ms,
before responding to external wake-up events, such as global resume, bus traffic, CS
active or LOW pulse on the D_SUSPEND/D_WAKEUP pin.
Figure 27
resume operations.
In
A — indicates the point at which the USB bus goes to the idle state.
B — after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode
register.
C — indicates resume condition, which can be a resume signal from the host, a LOW
pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.
3. In the interrupt service routine, the firmware must check the current status of the USB
4. To meet the suspend current requirements for a bus-powered device, internal clocks
5. When the firmware has set and cleared the GOSUSP bit of the DcMode register, the
Figure
b. All the input pins of the peripheral controller in the ISP1362 must have a CMOS
bus. When bit BUSTATUS of the DcInterrupt register is logic 0, the USB bus has left
suspend mode and the process must be aborted. Otherwise, the next step can be
executed.
must be switched off by clearing bit CLKRUN of the DcHardwareConfiguration
register.
peripheral controller in the ISP1362 enters the suspend state. It sets the
D_SUSPEND/D_WAKEUP pin to HIGH and switches off internal clocks after 2 ms.
logic 0 or logic 1 level.
27:
A
shows a typical timing diagram for the peripheral controller suspend and
> 3 ms
suspend
interrupt
Rev. 07 — 29 September 2009
idle state
> 5 ms
B
1.8 ms to
2.2 ms
C
0.5 ms to 3.5 ms
interrupt
resume
Single-chip USB OTG controller
D
10 ms
K-state
© ST-ERICSSON 2009. All rights reserved.
ISP1362
004aaa483
58 of 147
Related parts for ISP1362BDTM
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet:
Part Number:
Description:
Manufacturer:
STEricsson
Datasheet: