MMA8453QR1 Freescale, MMA8453QR1 Datasheet - Page 22

• Manufacturer Part Number: MMA8453QR1
• Manufacturer: Freescale

Specifications of MMA8453QR1

• Lead Free Status / RoHS Status: Compliant

Note: Auto-increment addresses which are not a simple increment are highlighted in bold. The auto-increment addressing is only enabled when
6.1
to application note, AN4076.
Table 11. Register Address Map
1. Register contents are preserved when transition from ACTIVE to STANDBY mode occurs.
2. Register contents are reset when transition from STANDBY to ACTIVE mode occurs.
3. Modification of this register’s contents can only occur when device is STANDBY mode except CTRL_REG1 ACTIVE bit and CTRL_REG2
22
MMA8453Q
0x00 STATUS: Data Status Register (Read Only)
Reserved (do not modify)
RST bit.
The following are the data registers for the MMA8453Q. For more information on data manipulation of the MMA8453Q, refer
ASLP_COUNT
PULSE_WIND
PULSE_TMLT
PULSE_LTCY
ZYXOW
CTRL_REG1
CTRL_REG2
CTRL_REG3
CTRL_REG4
CTRL_REG5
device registers are read using I
stop-bit is detected.
Bit 7
OFF_X
OFF_Y
OFF_Z
Data Registers
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
(1)(3)
ZOW
Bit 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x40 – 7F
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x26
0x27
0x28
0x29
0x30
0x31
2
C burst read mode. Therefore the internal storage of the auto-increment address is cleared whenever a
YOW
Bit 5
XOW
Bit 4
0x2A
0x2B
0x2C
0x2D
0x2E
0x0D
0x27
0x28
0x29
0x2F
0x30
0x31
—
ZYXDR
Bit 3
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Bit 2
ZDR
—
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
—
ODR = 800 Hz, STANDBY Mode.
Wake from Sleep, IPOL, PP_OD
Counter setting for Auto-SLEEP
Bit 1
YDR
Interrupt pin (INT1/INT2) map
Freescale Semiconductor
Reserved. Read return 0x00.
Window time for 2nd pulse
Latency time for 2
Sleep Enable, OS Modes,
Interrupt enable register
Time limit for pulse
X-axis offset adjust
Y-axis offset adjust
Z-axis offset adjust
RST, ST
Bit 0
nd
XDR
pulse
Sensors