MT28C6428P20FM-80 TET Micron Technology Inc, MT28C6428P20FM-80 TET Datasheet - Page 30

• Manufacturer Part Number: MT28C6428P20FM-80 TET
• Manufacturer: Micron Technology Inc

Specifications of MT28C6428P20FM-80 TET

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

STANDBY MODE
HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to I
device is deselected during an ERASE operation or dur-
ing programming, the device continues to draw cur-
rent until the operation is complete.
AUTOMATIC POWER SAVE (APS) MODE
ods when the Flash array is not being read and the
device is in the active mode. During this time the de-
vice switches to the automatic power save (APS) mode.
When the device switches to this mode, I
to a level comparable to I
be realized by applying a logic HIGH level on CE# to
place the device in standby mode. The low level of
power is maintained until another operation is initi-
ated. In this mode, the I/Os retain the data from the
last memory address read until a new address is read.
This mode is entered automatically if no addresses or
control signals toggle.
DEEP POWER-DOWN MODE
mand (see Table 3) it is possible to enable the DEEP
POWER-DOWN function. In this configuration, apply-
ing a logic LOW to RST# reduces the current to I
resets all the internal registers with the exception of the
individual block protection status. To exit this mode, a
wait time of 100µs (
HIGH is applied to RST#. During the wait time, the
device performs a full power-up sequence, and the
power consumption may exceed the standby current
limits.
F_V
VOLTAGES
programming and erase with F_V
range. In addition to the flexible block locking, the F_V
programming voltage can be held LOW for absolute
hardware write protection of all blocks in the Flash de-
vice. When F_V
operation results in an error, prompting the corre-
sponding status register bit (SR3) to be set.
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_4.p65 – Rev. 4, Pub. 10/02
I
Substantial power savings are realized during peri-
By issuing an ENABLE DEEP POWER-DOWN com-
The Flash memory devices provide in-system
CC
PP
supply current is reduced by applying a logic
/F_V
CC
PP
PROGRAM AND ERASE
is below V
t
RWHDP) must elapse after a logic
CC
PPLK
3
. Further power savings can
, any PROGRAM or ERASE
PP
CC
in the 0.9V–2.2V
3
(MAX). If the
CC
is reduced
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
CC
10
, and
PP
30
512K x 16 SRAM COMBO MEMORY
and erase with F_V
mum of 100 cycles and 10 cumulative hours. The de-
vice can withstand 100,000 WRITE/ERASE operations
when F_V
monitors the F_V
tions are allowed only when F_V
specified in Table 11.
WRITE/ERASE operation is prevented.
DEVICE RESET
be asserted (RST# = V
reset, the device can be accessed for a READ operation
with a delayed access time of
of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
to properly initialize internal chip operations:
should be brought to V
the rise time of RST# (10%–90%) should be < 10µs.
A factory option provides in-system programming
F_V
During WRITE and ERASE operations, the WSM
When F_V
To correctly reset the device, the RST# signal must
The following power-up sequence is recommended
• At power-up, RST# should be kept at V
• V
• F_V
When the power-up sequence is completed, RST#
In-Factory
In-System
DEVICE
after F_V
integrity.
PP
CC
Q should not come up before F_V
PP
at 12V ±5% (F_V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PP
should be kept at V
= F_V
CC
CC
is below V
F_V
PP
CC
reaches F_V
PP
.
voltage level. WRITE/ERASE opera-
PP
in the 0.0V–2.2V range.
Table 11
IL
IH
Ranges (V)
) for a minimum of
. To ensure proper power-up,
LKO
PP
2
MIN
11.4
t
) is supported for a maxi-
or F_V
0.9
RWH from the rising edge
CC
IL
PP
(MIN).
to maximize data
is within the ranges
PP
is below
©2002, Micron Technology, Inc.
CC
MAX
IL
12.6
t
2.2
.
VPPLK
RP. After
for 2µs
, any