MT48LC2M32B2P-6:G Micron Technology Inc, MT48LC2M32B2P-6:G Datasheet - Page 32

• Manufacturer Part Number: MT48LC2M32B2P-6:G
• Description: IC, SDRAM, 64MBIT, 166MHZ, TSOP-86
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC2M32B2P-6:G

• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 17/7.5/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Memory Type: DRAM - Sychronous
• Access Time: 5.5ns
• Page Size: 64Mbit
• Memory Case Style: TSOP
• No. Of Pins: 86
• Operating Temperature Range: 0°C To +70°C
• Frequency: 166MHz
• Supply Voltage: 3.3V
• Format - Memory: RAM
• Memory Size: 64M (2Mx32)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TFSOP (0.400", 10.16mm Width)
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Power-Down
Figure 24:
Figure 25:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
Terminating a WRITE Burst
PRECHARGE Command
Note:
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no refresh operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
A0–A9
BA0,1
RAS#
CAS#
ADDRESS
WE#
CKE
CLK
A10
CS#
DQMs are LOW.
CLK
DQ
TRANSITIONING DATA
HIGH
VALID ADDRESS
BANK,
COL n
WRITE
D
T0
n
IN
TERMINATE
Bank Selected
BURST
T1
All Banks
ADDRESS
BANK
COMMAND
DON’T CARE
(ADDRESS)
(DATA)
T2
NEXT
DON’T CARE
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS). See Figure 26 on page 33.
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands