MT48H4M16LFB4-75 IT:H Micron Technology Inc, MT48H4M16LFB4-75 IT:H Datasheet
MT48H4M16LFB4-75 IT:H
Specifications of MT48H4M16LFB4-75 IT:H
Related parts for MT48H4M16LFB4-75 IT:H
MT48H4M16LFB4-75 IT:H Summary of contents
Page 1
... Commercial (0°C to +70°C) – Industrial (–40°C to +85°C) • Die revision designator PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_1.fm - Rev. C 10/07 EN Products and specifications discussed herein are subject to change by Micron without notice. 64Mb: 4 Meg x 16 Mobile SDRAM Figure 1: 54-Ball VFBGA Ball Assignment (Top View ...
Page 2
... WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Electrical Specifications .39 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Timing Diagrams .45 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64Mb_x16_Mobile SDRAM_Y24LTOC.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2006 Micron Technology, Inc. All rights reserved. Table of Contents ...
Page 3
... WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Figure 49: 54-Ball VFBGA (8mm x 8mm .62 PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64Mb_x16_Mobile SDRAM_Y24LLOF.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2006 Micron Technology, Inc. All rights reserved. List of Figures ...
Page 4
... Specifications and Conditions (x16 .41 DD Table 15 Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 DD Table 16: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64Mb_x16_Mobile SDRAM_Y24LLOT.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2006 Micron Technology, Inc. All rights reserved. List of Tables ...
Page 5
... Figure 2: Part Numbering Diagram Example Part Number: MT48H4M16LFB4 MT48 1.8V/1.8V 54-ball VFBGA (8mm x 8mm) ”green” General Description The Micron containing 67,108,864 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’ ...
Page 6
... The temperature sensor is enabled by default and the PASR settings can be programmed through the extended mode register. SDRAM offers substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address ...
Page 7
... SDRAM_Y24L_2.fm - Rev. C 10/07 EN Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
Page 8
... Functional Description The 64Mb SDRAM (1 Meg banks quad-bank DRAM that operates at 1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...
Page 9
... Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with the burst length (BL) being programmable, as shown in Figure 4 on page 9. The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. BLs locations are available for both the sequential and the interleaved burst types ...
Page 10
... Meg x 16 Mobile SDRAM Mode Register Definition Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 11
... READ NOP NOP MRD before initiating any subsequent operation. Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 64Mb: 4 Meg x 16 Mobile SDRAM Mode Register Definition NOP OUT Don’t Care Undefined ©2006 Micron Technology, Inc. All rights reserved. ...
Page 12
... PASR. Temperature–Compensated Self Refresh (TCSR) On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. Therefore recom- mended not to program or use the TCSR control bits in the extended mode register. ...
Page 13
... Quarter-drive strength is intended for lighter loads or point-to-point systems. PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM Mode Register Definition Micron Technology, Inc., reserves the right to change products or specifications without notice. 13 ...
Page 14
... However, the DQ column reads a “Don’t Care” state to illustrate that the BURST TERMINATE command can occur when there is no data present. PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM CS# RAS# CAS# WE# DQM H ...
Page 15
... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...
Page 16
... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down, as long as power is not completely removed from the SDRAM. When in the self refresh mode, the SDRAM retains data without external clocking ...
Page 17
... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for required for the completion of any internal refresh in progress ...
Page 18
... Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 7). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be ...
Page 19
... This is shown in Figure 10 on page 20 for and data element either the last of a burst of four or the last desired of a longer burst. The Mobile SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command ...
Page 20
... READ NOP NOP NOP READ NOP cycles Bank, Bank, Col n Col OUT OUT Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 64Mb: 4 Meg x 16 Mobile SDRAM T6 NOP NOP D D OUT OUT NOP NOP OUT OUT OUT ...
Page 21
... OUT OUT READ READ READ READ Bank, Bank, Bank, Bank, Col n Col a Col x Col m D OUT Transitioning Data 21 64Mb: 4 Meg x 16 Mobile SDRAM T4 T5 NOP NOP D D OUT OUT NOP NOP NOP OUT OUT OUT Don’t Care met. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 22
... PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/ CLK DQM READ NOP NOP Bank, Col n DQ Transitioning Data READ NOP NOP Bank, Col n DQ Transitioning Data 22 64Mb: 4 Meg x 16 Mobile SDRAM T3 T4 NOP WRITE Bank, Col OUT Don’t Care NOP NOP WRITE Bank, ...
Page 23
... T3 T4 BURST READ NOP NOP NOP TERMINATE cycles Bank, Col OUT OUT Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 64Mb: 4 Meg x 16 Mobile SDRAM Operations NOP NOP ACTIVE Bank a, Row D OUT NOP NOP ACTIVE Bank a, ...
Page 24
... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 19 on page 26. Data either the last of a burst of two or the last desired of a longer burst. The Mobile SDRAM uses a pipe- lined architecture and therefore does not require the 2n rule associated with a prefetch architecture ...
Page 25
... WRITE Bank, Bank, Col n Col Transitioning Data Don’t Care 25 64Mb: 4 Meg x 16 Mobile SDRAM T3 NOP t WR after the clock edge at which Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Operations ...
Page 26
... WRITE NOP READ Bank, Bank, Col n Col Transitioning Data 26 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP NOP D D OUT OUT Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
Page 27
... CLK BURST NEXT WRITE TERMINATE COMMAND Bank, (Address) Col (Data Transitioning Data Don’t Care 27 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP ACTIVE Bank a , Row t RP NOP NOP ACTIVE Bank a , Row Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 28
... BANK ADDRESS Valid Address Don’t Care t CKS). See Figure 24 on page 29. Micron Technology, Inc., reserves the right to change products or specifications without notice. 28 64Mb: 4 Meg x 16 Mobile SDRAM Operations t RP) after the PRECHARGE command is ©2006 Micron Technology, Inc. All rights reserved. ...
Page 29
... CKE is LOW. CKE must be held LOW during deep power-down. To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of deep power- down mode, a full Mobile SDRAM initialization sequence is required. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “ ...
Page 30
... PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/ NOP WRITE Bank, Col Transitioning Data READ NOP NOP Bank, Col n D OUT n Transitioning Data 30 64Mb: 4 Meg x 16 Mobile SDRAM NOP NOP Don’t Care NOP NOP NOP OUT OUT OUT Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
Page 31
... Concurrent Auto Precharge Micron SDRAM devices support concurrent auto precharge, which enables an access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing. Four cases where concurrent auto precharge occurs are defined below ...
Page 32
... Col a 1 DQM (Bank from contending with D OUT t WR begins when the WRITE to bank m is registered. The last valid Micron Technology, Inc., reserves the right to change products or specifications without notice. 32 64Mb: 4 Meg x 16 Mobile SDRAM Operations WRITE - AP NOP NOP NOP NOP ...
Page 33
... NOP Bank n Bank n Page active WRITE with Page active Bank m Bank n , Address Col Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 64Mb: 4 Meg x 16 Mobile SDRAM Read - AP NOP NOP NOP NOP Bank m Interrupt burst, Write-back Precharge Bank Bank n t ...
Page 34
... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...
Page 35
... Starts with registration of a WRITE command with auto precharge enabled and ends when be in the idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 64Mb: 4 Meg x 16 Mobile SDRAM Operations is HIGH (see Table 6 on page 34) and has been met. ...
Page 36
... Meg x 16 Mobile SDRAM Starts with registration of an AUTO REFRESH command and ends when t t RFC is met. After RFC is met, the SDRAM will be in the all banks idle state. Starts with registration of a LOAD MODE REGISTER command and ends t t when MRD has been met ...
Page 37
... Starts with registration of a WRITE command with auto precharge enabled and ends when be in the idle state. 37 64Mb: 4 Meg x 16 Mobile SDRAM is HIGH (see Table 6 on page 34) and has been met. t RCD has been met. No data ...
Page 38
... Figure 30 on page 33). The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM t WR begins when the READ to bank m is registered. The last valid WRITE t ...
Page 39
... SDRAM_Y24L_2.fm - Rev. C 10/07 EN Symbol Symbol -100µ 100µ ≤ OUT Symbol 39 64Mb: 4 Meg x 16 Mobile SDRAM Electrical Specifications Min Max /V Q –0.35 +2 –0.35 +2 –55 +150 STG Q = 1.7–1.95V Min Max Units 1.7 1.95 Q 1.7 1.95 0.8 × 0 –0.3 +0.3 IL 0.9 × ...
Page 40
... Refresh period (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH-to-ACTIVE command PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN 64Mb: 4 Meg x 16 Mobile SDRAM -75 Symbol Min Max (3) – ...
Page 41
... DQD t DQM t DQZ t DWD t DAL t DPL t BDL t CDL t RDL t MRD ROH( ROH(2) DD Symbol (MIN RFC = RFC (MIN RFC = 15.625µ Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 64Mb: 4 Meg x 16 Mobile SDRAM Electrical Specifications -75 -8 Units 1.7V–1.95V 1.7V– ...
Page 42
... Bank, 1/4 Bank -50 -40 -30 -20 - Symbol 64Mb: 4 Meg x 16 Mobile SDRAM Electrical Specifications / 1.7–1.95V DD DD -75/-8 180 120 130 80 100 80 100 80 100 Temperature (C) Min Max 1.5 4.0 1.5 4.0 3.0 6.0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 43
... 7.5ns for -75 and CK = 8.0ns for - for a pulse width ≤3ns, and the pulse width overshoot: V (MAX 64Mb: 4 Meg x 16 Mobile SDRAM Q = 1.7–1.95V 25°C; pin under test biased at A ≤ +70°C for commercial parts; A and REF refresh require- and monotonic manner ...
Page 44
... WR, and PRECHARGE commands). CKE may be 6 limit is actually a nominal value and does not result in a fail value. 7 85°C are guaranteed for the entire temperature range. All other 64Mb: 4 Meg x 16 Mobile SDRAM t WR. During auto t RP) begins at 7.5ns for -75, and 7ns t RFC (MIN) else CKE is LOW ...
Page 45
... All Banks ( ( ( ( ) ) ) ) ( ( ( ( ) ) ) ) RFC RP Precharge all banks Micron Technology, Inc., reserves the right to change products or specifications without notice. 45 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams LMR LMR VALID ( ( ( ( ( ( ) ...
Page 46
... Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/ CKS NOP NOP ( ( ( ( ( ( Input buffers gated off while in power-down mode Exit power-down mode 46 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams CKS ( ( ) ) ( ( ) ...
Page 47
... NOP NOP NOP OUT OUT t LZ Micron Technology, Inc., reserves the right to change products or specifications without notice. 47 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP WRITE NOP Column e 2 Bank OUT OUT Don’t Care Undefined ©2006 Micron Technology, Inc. All rights reserved. ...
Page 48
... RP t RFC 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams AUTO NOP NOP ACTIVE REFRESH ( ( ) ) ( ( ) ) ( ...
Page 49
... XSR Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams AUTO 1 REFRESH Don’t Care ©2006 Micron Technology, Inc. All rights reserved. ...
Page 50
... A8, A9, and A11 = “Don’t Care.” PDF: 09005aef8237ed98/Source: 09005aef8237ed68 64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/ READ NOP NOP t CMH 2 Column m Bank OUT OUT t LZ CAS latency 50 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP NOP ACTIVE PRECHARGE Row All banks Row Single banks Bank(s) Bank OUT ...
Page 51
... SDRAM_Y24L_2.fm - Rev. C 10/ READ NOP NOP t CMS t CMH Column m 2 Bank OUT t LZ CAS latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP NOP NOP ACTIVE Row Row Bank ...
Page 52
... Column m All banks Single banks Bank Bank( OUT CAS latency 52 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams ACTIVE NOP NOP Row Row Bank t RP Don’t Care Undefined t RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 53
... NOP 3 NOP 3 READ NOP t CMS t CMH Column m 2 Enable auto precharge Bank CAS latency t RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP ACTIVE NOP Row Row Bank ...
Page 54
... SDRAM_Y24L_2.fm - Rev. C 10/ READ NOP ACTIVE t CMS t CMH 2 Row Column m Row Bank 0 Bank OUT t LZ CAS latency - Bank 0 t RCD - Bank 3 54 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP READ NOP ACTIVE Column b 2 Row Enable auto precharge Row Bank 3 Bank ...
Page 55
... READ NOP NOP t CMS t CMH Column m 2 Bank OUT CAS latency 55 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP NOP NOP OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. ...
Page 56
... 3> and the PRECHARGE command, regardless of fre 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP PRECHARGE NOP All banks Single bank Bank Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. T9 ACTIVE ...
Page 57
... WRITE NOP NOP NOP t CMH Bank 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. T9 ACTIVE Row Row Bank Don’t Care ...
Page 58
... NOP 4 NOP 4 WRITE t CMH Column m 3 Bank m> and the PRECHARGE command, regardless of frequency 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams PRECHARGE NOP ACTIVE All banks Row Single bank Bank Bank RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 59
... Enable Auto Precharge Bank m> and the PRECHARGE command, regardless of frequency RAS would be violated. 59 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams ACTIVE NOP NOP Row Row Bank t RP Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 60
... WRITE NOP ACTIVE NOP t CMH Row Row Bank 0 Bank RCD - Bank 1 60 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams WRITE NOP NOP Column b 2 Enable auto precharge Bank Bank Bank 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 61
... Column m 2 Enable auto precharge Disable auto precharge Bank Micron Technology, Inc., reserves the right to change products or specifications without notice. 61 64Mb: 4 Meg x 16 Mobile SDRAM Timing Diagrams T5 T6 NOP NOP ©2006 Micron Technology, Inc. All rights reserved. T7 NOP Don’t Care ...
Page 62
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 62 64Mb: 4 Meg x 16 Mobile SDRAM Package Dimensions Solder ball material: 96.5% Sn, 3% Ag, 0.5% CU Solder mask defined ball pads: Ø0.40 Substrate material: Plastic laminate Mold compound: Epoxy novolac Ball ...