MT41J256M4JP-15E:G Micron Technology Inc, MT41J256M4JP-15E:G Datasheet - Page 126

• Manufacturer Part Number: MT41J256M4JP-15E:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT41J256M4JP-15E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

MPR Read Predefined Pattern
MODE REGISTER SET (MRS)
ZQ CALIBRATION
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The
following is an example of using the read out predetermined read calibration pattern.
The example is to perform multiple reads from the multipurpose register in order to do
system level read timing calibration based on the predetermined and standardized
pattern.
The following protocol outlines the steps used to perform the read calibration:
• Precharge all banks
• After
• Data WRITE operations are not allowed until the MPR returns to the normal DRAM
• Issue a read with burst order information (all other address pins are “Don’t Care”):
• After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern
• The memory controller repeats the calibration reads until read data capture at
• After the last MPR READ burst and after
• When
The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode
register is programmed:
• BA2 = 0, BA1 = 0, BA0 = 0 for MR0
• BA2 = 0, BA1 = 0, BA0 = 1 for MR1
• BA2 = 0, BA1 = 1, BA0 = 0 for MR2
• BA2 = 0, BA1 = 1, BA0 = 1 for MR3
The MRS command can only be issued (or reissued) when all banks are idle and in the
precharged state (
wait the specified time
VATE command (see Figure 52 on page 108). There is also a restriction after issuing an
MRS command with regard to when the updated functions become available. This
parameter is specified by
Figure 52 on page 108 and Figure 53 on page 109. Violating either of these requirements
will result in unspecified operation.
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R
and ODT values (R
240Ω (±1 percent) external resistor is connected from the DRAM’s ZQ ball to V
quent reads and loads the predefined pattern into the MPR. As soon as
t
state
– A[1:0] = 00 (data burst order is fixed starting at nibble)
– A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
– A12 = 1 (use BL8)
(0, 1, 0, 1, 0, 1, 0, 1)
memory controller is optimized
MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subsequent
read and write accesses will be regular reads and writes from/to the DRAM array
(such as activate a memory bank for regular read or write access) are permitted
MOD are satisfied, the MPR is available
t
RP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subse-
t
MRD and
t
RP is satisfied and no data bursts are in progress). The controller must
TT
t
MOD are satisfied from the last MRS, the regular DRAM commands
) over process, voltage, and temperature, provided a dedicated
t
MRD before initiating a subsequent operation such as an ACTI-
t
MOD. Both
126
t
MRD and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
MPRR has been satisfied, issue MRS,
1Gb: x4, x8, x16 DDR3 SDRAM
t
MOD parameters are shown in
©2006 Micron Technology, Inc. All rights reserved.
Operations
t
MRD and
SS
Q.
ON
)