MT45V512KW16PEGA-70 WT Micron Technology Inc, MT45V512KW16PEGA-70 WT Datasheet - Page 6

• Manufacturer Part Number: MT45V512KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V512KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Ball Descriptions
Table 1:
PDF: 09005aef82f264f6/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. C 4/08 EN
H4, H3, H2, D4,
F3, G4, G3, H5,
D2, C2, C1, B1,
H1, D3, E4, F4,
C4, C3, B4, B3,
G1, F1, F2, E2,
G6, F6, F5, E5,
D5, C6, C5, B6
Assignment
VFBGA Ball
A5, A4, A3
E3, G2, H6
B5
A1
A2
B2
G5
A6
D6
D1
E1
E6
VFBGA Ball Descriptions
DQ[15:0]
Symbol
A[18:0]
V
V
WE#
OE#
UB#
CE#
LB#
ZZ#
V
V
NC
CC
SS
CC
SS
Q
Q
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Type
–
Description
Address inputs: Inputs for the address accessed during READ or WRITE operations.
The address lines are also used to define the value to be loaded into the CR.
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Lower byte enable: DQ[7:0].
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Upper byte enable: DQ[15:8].
Write enable: Enables WRITE operations when LOW.
Sleep enable: When ZZ# is LOW, the CR can be loaded, or the device can enter one
of two low-power modes (DPD or PAR).
Data inputs/outputs.
Device power supply (2.7–3.6V): Power supply for device core operation.
I/O power supply (2.7–3.6V): Power supply for input/output buffers.
V
V
No connect: Not internally connected.
SS
SS
Q must be connected to ground.
must be connected to ground.
8Mb: 3.0V Core Async/Page PSRAM Memory 512K x 16
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Ball Descriptions