MT45W2MW16PFA-70 Micron Technology Inc, MT45W2MW16PFA-70 Datasheet - Page 11

• Manufacturer Part Number: MT45W2MW16PFA-70
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PFA-70

• Lead Free Status / RoHS Status: Not Compliant

Low-Power Operation
Standby Mode Operation
Temperature-Compensated Refresh
Partial-Array Refresh
PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f
AsyncCellularRAM_2.fm - Rev. G 10/05 EN
During standby, the device current consumption is reduced to the level necessary to per-
form the DRAM refresh operation on the full array. STANDBY operation occurs when
CE# and ZZ# are HIGH.
The device will enter a reduced power state during READ and WRITE operations where
the address and control inputs remain static for an extended period of time. This mode
will continue until a change occurs to the address or control inputs.
Temperature-compensated refresh is used to adjust the refresh rate depending on the
device operating temperature. DRAM technology requires more frequent REFRESH
operations to maintain data integrity as temperatures increase. More frequent refresh is
required due to the increased leakage of the DRAM’s capacitive storage elements as tem-
peratures rise. A decreased refresh rate at lower temperatures will facilitate a savings in
standby current.
TCR allows for adequate refresh at four different temperature thresholds: +15°C, +45°C,
+70°C, and +85°C. The setting selected must be for a temperature higher than the case
temperature of the CellularRAM device. For example, if the case temperature is +50°C,
the system can minimize self refresh current consumption by selecting the +70°C set-
ting. The +15°C and +45°C settings would result in inadequate refreshing and cause data
corruption.
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the system to reduce refresh current by only refreshing that
part of the memory array that is absolutely necessary. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. Data stored in
addresses not receiving refresh will become corrupted. The mapping of these partitions
can start at either the beginning or the end of the address map (see Table 3 on page 15).
READ and WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] =
1). PAR can be initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning
ZZ# to HIGH will cause an exit from PAR and the entire array will be immediately avail-
able for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software access sequence (see Software
Access to the Configuration Register on page 13). PAR is enabled immediately upon set-
ting CR[4] to “1” using this method. However, using software access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ# contin-
ues to enable WRITEs to the CR. This functional change persists until the next time the
device is powered up. (See Figure 8.)
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150µs initialization process. During
this 150µs period, the current consumption will be higher than the specified standby
levels but considerably lower than the active current specification.
Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has
been set HIGH (CR[4] = 1).
The device should not be put into DPD using CR software access.
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2003 Micron Technology, Inc. All rights reserved.