MT45W2MW16PFA-70 Micron Technology Inc, MT45W2MW16PFA-70 Datasheet - Page 5

• Manufacturer Part Number: MT45W2MW16PFA-70
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PFA-70

• Lead Free Status / RoHS Status: Not Compliant

General Description
Figure 2:
PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f
AsyncCellularRAM_2.fm - Rev. G 10/05 EN
WE#
Functional Block Diagram: 4 Meg x 16
OE#
UB#
CE#
LB#
ZZ#
A[21:0]
Note:
Control
Logic
Micron
for low-power, portable applications. The MT45W4MW16PFA is a 64Mb DRAM core
device organized as 4 Meg x 16 bits. This device includes the industry-standard, asyn-
chronous memory interface found on other low-power SRAM or Pseudo SRAM offerings.
Operating voltages have been reduced in an effort to minimize power consumption. The
core voltage has been reduced to a 1.80V operating level. To maintain compatibility with
different memory bus interfaces, CellularRAM devices are available with I/O voltages of
3.0V, 2.5V, or 1.8V.
A user-accessible configuration register (CR) defines how the CellularRAM device per-
forms on-chip refresh and whether page mode read accesses are permitted. This register
is automatically loaded with a default setting during power-up and can be updated at
any time during normal operation.
To operate seamlessly on an asynchronous memory bus, CellularRAM products incor-
porate a transparent self refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
Special attention has been focused on current consumption during self refresh. Cellular-
RAM products include three system-accessible mechanisms used to minimize refresh
current. Temperature-compensated refresh (TCR) is used to adjust the refresh rate
according to the case temperature. The refresh rate can be decreased at lower tempera-
tures to minimize current consumption during standby. Setting sleep enable (ZZ#) to
LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-
down (DPD). PAR limits refresh to only that part of the DRAM array that contains essen-
tial data. DPD halts refresh operation altogether and is used when no vital information is
stored in the device. These three refresh mechanisms are accessed through the CR.
Functional block diagrams illustrate simplified device operation. See truth table, ball
descriptions, and timing diagrams for detailed information.
®
CellularRAM™ products are high-speed, CMOS PSRAM memories developed
Address Decode
Configuration
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory
Register (CR)
Logic
5
4,096K x 16
Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DRAM
Array
Output
Buffers
Input/
MUX
and
General Description
©2003 Micron Technology, Inc. All rights reserved.
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