M48T513V-85CS1 STMicroelectronics, M48T513V-85CS1 Datasheet - Page 11

• Manufacturer Part Number: M48T513V-85CS1
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48T513V-85CS1

• Word Size: 8b
• Organization: 512x8
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 85ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 60mA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

READ Mode
The M48T513Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 524,272
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within t
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
Figure 8. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
Figure 9. Address Controlled, READ Mode AC Waveforms
A0-A16
E
G
DQ0-DQ7
A0-A16
DQ0-DQ7
DATA VALID
tAXQX
tAVQV
tELQX
AVQV
tGLQX
tELQV
tAVQV
tGLQV
(Ad-
tAVAV
VALID
tAVAV
VALID
the latter of the Chip Enable Access Times (t
or
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for t
Data Hold Time) but will go indeterminate until the
next Address Access.
Output
DATA OUT
AVQV
Enable
tAXQX
, the data lines will be driven to an
DATA VALID
tGHQZ
M48T513Y, M48T513V
Access
AVQV
. If the Address In-
Time
tEHQZ
AI01197
AI02324
AXQX
(t
(Output
GLQV
ELQV
11/31
).
)