M48T513V-85CS1 STMicroelectronics, M48T513V-85CS1 Datasheet - Page 16

• Manufacturer Part Number: M48T513V-85CS1
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48T513V-85CS1

• Word Size: 8b
• Organization: 512x8
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 85ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 60mA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

M48T513Y, M48T513V
Table 10. Power Down/Up Trip Points DC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
CLOCK OPERATIONS
TIMEKEEPER Registers
The M48T513Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data (see Table 11,
page 17). These registers are memory locations
which contain external (user accessible) and inter-
nal copies of the data (usually referred to as Bi-
PORT
copies are independent of internal functions ex-
cept that they are updated periodically by the si-
multaneous transfer of the incremented internal
copy. TIMEKEEPER and Alarm Registers store
data in BCD.
Reading the Clock
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a ’1’ is written to the
READ Bit, D6 in the Control Register (7FFF8h). As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af-
ter the READ Bit is reset to a ’0.’
16/31
Symbol
t
V
DR
V
2. All voltages referenced to V
3. At 25 C.
PFD
SO
(3)
TIMEKEEPER cells). The external
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage
Expected Data Retention Time
SS
Parameter
.
(1,2)
A
= 0 to 70 C; V
TIME-
M48T513Y
M48T513V
M48T513Y
M48T513V
CC
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a ’1’, like the
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table Figure 11, page 17).
Resetting the WRITE Bit to a ’0’ then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to the actual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to ’0.’
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 7FFF9h. Setting it to
a ’1’ stops the oscillator. When reset to a ’0,’ the
M48T513Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
= 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
Min
4.2
2.7
10
V
PFD
4.35
Typ
2.9
3.0
–100mV
Max
4.5
3.0
YEARS
Unit
V
V
V