IDT71321SA55JG IDT, Integrated Device Technology Inc, IDT71321SA55JG Datasheet - Page 10

IDT71321SA55JG

Manufacturer Part Number
IDT71321SA55JG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71321SA55JG

Density
16Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
11b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
155mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
2K
Lead Free Status / RoHS Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71321SA55JG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71321SA55JG
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT71321SA55JGI
Manufacturer:
IDT
Quantity:
4
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)
ADDRESS
ADDRESS
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
DATA
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
DATA
DATA
Load (Figure 2).
placed on the bus for the required t
as the specified t
WR
R/W
R/W
is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
OUT
CE
OE
CE
IN
IN
WP
.
t
AS
t
EW
AS
DW
(6)
(6)
or t
. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
WP
(4)
) of CE = V
IL
t
WZ
and R/W= V
(7)
t
AW
t
AW
IL
t
WC
.
t
WC
t
WP
6.42
t
10
(2)
EW
(2)
t
DW
t
DW
WP
or (t
Industrial and Commercial Temperature Ranges
WZ
+ t
DW
t
WR
) to allow the I/O drivers to turn off data to be
(3)
t
WR
t
DH
(3)
t
OW
t
DH
(1,5)
t
HZ
(1,5,8)
(7)
t
HZ
(7)
(4)
2691 drw 09
2691 drw 08

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