TXN174310850F16 Intel, TXN174310850F16 Datasheet - Page 11

• Manufacturer Part Number: TXN174310850F16
• Manufacturer: Intel

Specifications of TXN174310850F16

• Optical Fiber Type: TX/RX
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Mounting: Screw
• Lead Free Status / RoHS Status: Compliant

Intel
Table 7.
5.0
Table 8.
2-Nov-2007
Document Number: 306424-005
®
TXN17431 (0850) Optical Transceiver
Digital Control and Monitoring Signals
Data Output/Input Configuration
The TXN17431 Optical Transceiver is fully compliant with IEEE 802.3ae standards for
XAUI data format.
for the TXN17431 Optical Transceiver.
Data Input/Output Configuration (Sheet 1 of 2)
Management
data interface
Management
data clock
Input pins for
setting module
port address
Link alarm
status
interrupt
Transmitter
on/off
Module reset
Module detect
Adaptive
power supply
APS sense
connection
APS
configuration
TX LANE0+
TX LANE0-
TX LANE1+
TX LANE1-
TX LANE2+
TX LANE2-
TX LANE3+
TX LANE3-
RX LANE0+
RX LANE0-
Function
Pin Name
Intel
MOD DETECT
APS_SENSE
TX ON/OFF
Pin Name
In/Out
APS_SET
PRTAD
RESET
MDIO
Out
®
LASI
MDC
APS
Table 8
In
In
In
In
TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA
Transmitter XAUI input differential
pair—Lane 0
Transmitter XAUI input differential
pair—Lane 1
Transmitter XAUI input differential
pair—Lane 2
Transmitter XAUI input differential
pair—Lane 3
Receiver XAUI output differential
pair—Lane 0
lists the I/O configuration.
19–23
28–29
Pin #
7-8
17
18
12
10
14
27
25
9
Description
Digital interface provides
access to management data
as specified in IEEE 802.3ae
XAUI interface specifications
and XENPAK MSA
Clock for management data
interface
Allows the MDIO address to
be set
Logic low indicates status
interrupt triggered, logic
high indicates normal
operation
Turns off laser. Optical
output power with laser
turned off is less than -30
dBm.
Logic high for normal
operation, logic low for reset
Indicates presence of
module
Adaptive power supply input
Adaptive power supply
voltage select pin
Feedback input for APS
Description
Table 9
Compliant with IEEE 802.3ae clause 47
Compliant with IEEE 802.3ae clause 47
Compliant with IEEE 802.3ae clause 47
Compliant with IEEE 802.3ae clause 47
Compliant with IEEE 802.3ae clause 47
1.2 V CMOS compatible
1.2 V CMOS compatible
1.2 V CMOS compatible
Open drain compatible
10–22 k pull-up on host
1.2 V CMOS compatible
Open drain compatible
14.7 k pull-up on transceiver
1.2 V CMOS compatible
Open drain compatible
14.7 K pull-up on transceiver
1.2 V CMOS compatible
Connected to signal ground inside
module through 1 KΩ resistor
The device requires 1.8V at these
pins.
This pin is a direct sense of the
APS voltage on pins 7–8 and
28–29 at an internal point
This pin will be connected to the
ground inside module to direct an
adaptive power supply to provide
1.8 V.
lists the complete pinout
Logic
Interface
Datasheet
11