TXN174310850F16 Intel, TXN174310850F16 Datasheet - Page 15

• Manufacturer Part Number: TXN174310850F16
• Manufacturer: Intel

Specifications of TXN174310850F16

• Optical Fiber Type: TX/RX
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Mounting: Screw
• Lead Free Status / RoHS Status: Compliant

Intel
Table 10.
6.3
2-Nov-2007
Document Number: 306424-005
®
TXN17431 (0850) Optical Transceiver
Note: A single read only or write only does not automatically increment the address.
MDIO Frame Format
MDIO Register Set
This section provides information on the location and functionality of the TXN17431
Optical Transceiver Registers. The MDIO Register set is divided into the following five
register sections:
Unique device IDs address the various registers.
Abbreviations under the register Access column are described as follows:
ADDRESS
WRITE
READ
READ INC
Abbreviation
1. Preamble (PRE): A pattern of 32 logic one bits used for clock and data synchronization.
2. Start of Frame (ST): Two bit logic 0 ensures transitions from default logic one to zero.
3. Opcode: Indicates the MDIO transaction type. “00” indicates register addressing command, “01” indicates
4. PRTAD: A 5-bit port address set through PRTAD[4:0] pins at the connector level.
5. DID: Device address is 5 bits but only valid combinations are “00001” for accessing PMA/PMD, “00011” for
6. TA: Two bit time spacing between the addressing and data fields to avoid contention during a read
7. AD: This address/data field is 16 bits; the most significant bit is transmitted/received first.
8. IDLE: MDIO high impedance state will disable all three state drivers.
•
•
•
•
•
Transaction Type
write data to register command, “11” indicates read data from register command, “10” indicates read data
return and address increment.
accessing PCS and “00100” for accessing PHY XS.
transaction.
R/W, SC
“PMA/PMD Control Registers (Device ID = 1h)” on page 17
Physical Medium Attachment/Physical Medium Dependent (PMA/PMD) control
“PCS Control Registers (Device ID = 3h)” on page 22
Physical Coding Sublayer (PCS) control
“PHY_XS Control Registers (Device ID = 4h)” on page 26
XGMII Extender Sublayer (PHY XGXS) control
“XENPAK NVR Registers and NVR EEPROM Description” on page 30
“XENPAK DOM/LASI Control and Status Registers” on page 31
RO, LH
RO, LL
R/W
RO
Register Access Description
Read only register: Writes are ignored
Read and write register: Reads and writes are allowed with the proper read/write
sequence
Read only register: The latched low bit is reset to high by a read unless the input low state
is present
Self clearing read/write register: The bit clears itself after transaction
Read only register: Latched high bit is reset to low by a read unless the input high state is
present
Intel
®
TXN17431 (0850) 10.3 Gbps 850 nm Optical Transceiver Compliant with XENPAK MSA
PRE
1…1
1…1
1…1
1…1
1
ST
00
00
00
00
2
Opcode
00
01
11
10
3
PRTAD[4:0]
PRTAD[4:0]
PRTAD[4:0]
PRTAD[4:0]
PRTAD
4
DID[4:0]
DID[4:0]
DID[4:0]
DID[4:0]
DID
5
TA
Z0
Z0
10
10
6
AD[15:0]
AD[15:0]
AD[15:0]
AD[15:0]
AD
7
Datasheet
IDLE
Z
Z
Z
Z
8
15