ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 11
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ISP1760BEGA
Manufacturer Part Number
ISP1760BEGA
Description
Manufacturer
STEricsson
Datasheet
1.ISP1760BEGA.pdf
(105 pages)
Specifications of ISP1760BEGA
Package Type
LQFP
Pin Count
128
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1760BEGA
Manufacturer:
LEVELONE
Quantity:
450
Part Number:
ISP1760BEGA
Manufacturer:
ST
Quantity:
20 000
Table 2.
CD00222702
Product data sheet
Symbol
CS_N
RD_N
WR_N
GNDD
BAT_ON_N
n.c.
IRQ
n.c.
DREQ
V
DACK
TEST3
REG1V8
SUSPEND/
WAKEUP_N
TEST4
GNDC
RESET_N
GNDA
TEST5
TEST6
CC(I/O)
[1][2]
Pin description
Pin
LQFP128
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
…continued
A12
B12
B11
A11
C10
A10
B10
A9
B9
C8
A8
B8
B7
A7
C6
A6
B6
B5
A5
B4
TFBGA128
Type
I
I
I
-
OD
-
O
-
O
P
I
-
P
I/OD
-
-
I
-
-
-
[3]
Rev. 08 — 13 April 2010
Description
chip select signal assertion indicates the ISP1760 being accessed;
active LOW
input, 3.3 V tolerant
read enable; active LOW
input, 3.3 V tolerant
write enable; active LOW
input, 3.3 V tolerant
digital ground
to indicate the presence of a minimum 3.3 V on pins 6 and 7
(open-drain); connect to V
output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant
not connected
host controller interrupt signal
output pad, 4 mA drive, 3.3 V tolerant
not connected
DMA controller request for the host controller
output pad, 4 mA drive, 3.3 V tolerant
digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling
capacitor; see
host controller DMA request acknowledgment; when not in use,
connect to V
input, 3.3 V tolerant
connect to V
core power output (1.8 V); internal 1.8 V for the digital core; used for
decoupling; connect a 100 nF capacitor; for details on additional
capacitor placement, see
host controller suspend and wake-up; 3-state suspend output (active
LOW) and wake-up input circuits are connected together
connect to V
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
pull up to V
core ground
external power-up reset; active LOW; when reset is asserted, it is
expected that bus signals are idle, that is, not toggling
input, 3.3 V tolerant
Remark: During reset, ensure that all the input pins to the ISP1760
are not toggling and are in their inactive states.
analog ground
connect a 220 nF capacitor between this pin and pin 125
connect a 220 nF capacitor between this pin and pin 124
•
•
HIGH = output is 3-state; ISP1760 is in suspend mode
LOW = output is LOW; ISP1760 is not in suspend mode
CC(I/O)
CC(I/O)
CC(I/O)
CC(I/O)
Section 7.8
through a 10 kΩ pull-up resistor
through a 10 kΩ pull-up resistor
through an external 10 kΩ pull-up resistor
Embedded Hi-Speed USB host controller
Section 7.8
CC(I/O)
through a 10 kΩ pull-up resistor
© ST-ERICSSON 2010. All rights reserved.
ISP1760
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