ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 44
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ISP1760BEGA
Manufacturer Part Number
ISP1760BEGA
Description
Manufacturer
STEricsson
Datasheet
1.ISP1760BEGA.pdf
(105 pages)
Specifications of ISP1760BEGA
Package Type
LQFP
Pin Count
128
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1760BEGA
Manufacturer:
LEVELONE
Quantity:
450
Part Number:
ISP1760BEGA
Manufacturer:
ST
Quantity:
20 000
Table 42.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Buffer Status register (address 0334h) bit allocation
8.3.6 Buffer Status register
R/W
R/W
R/W
R/W
31
23
15
7
0
0
0
0
The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is,
ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets
the Buffer Filled bit of a particular transfer in the Buffer Status register, the HC will start
traversing through PTD headers that are not marked for skipping and are valid PTDs.
Remark: Software can set these bits during the initialization.
Table 42
Table 43.
Bit
31 to 3 -
2
1
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
Symbol
ISO_BUF_
FILL
INT_BUF_
FILL
shows the bit allocation of the Buffer Status register.
Buffer Status register (address 0334h) bit description
reserved
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
reserved
ISO Buffer Filled:
1 — Indicates one of the ISO PTDs is filled, and the ISO PTD area will be
processed.
0 — Indicates there is no PTD in this area. Therefore, processing of the ISO
PTDs will completely be skipped.
INT Buffer Filled:
1 — Indicates one of the INT PTDs is filled, and the INT PTD area will be
processed.
0 — Indicates there is no PTD in this area. Therefore, processing of the INT
PTDs will completely be skipped.
Rev. 08 — 13 April 2010
[1]
R/W
R/W
R/W
R/W
28
20
12
4
0
0
0
0
reserved
reserved
reserved
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
ISO_BUF_
R/W
R/W
R/W
FILL
R/W
26
18
10
0
0
0
2
0
INT_BUF_
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
FILL
R/W
25
17
0
0
9
0
1
0
ISP1760
ATL_BUF_
FILL
R/W
R/W
R/W
R/W
44 of 105
24
16
0
0
8
0
0
0