ISP1760ET STEricsson, ISP1760ET Datasheet - Page 46
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ISP1760ET
Manufacturer Part Number
ISP1760ET
Description
Manufacturer
STEricsson
Datasheet
1.ISP1760ET.pdf
(111 pages)
Specifications of ISP1760ET
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NXP Semiconductors
[1]
Table 44.
ISP1760_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 0
The reserved bits should always be written with the reset value.
ATL Done Timeout register (address 0338h) bit description
Symbol
ATL_DONE_
TIMEOUT[31:0]
8.3.7 ATL Done Timeout register
8.3.8 Memory register
R/W
7
0
Table 43.
The bit description of the ATL Done Timeout register is given in
The Memory register contains the base memory read address and the respective bank.
This register needs to be set only before a first memory read cycle. Once written, the
address will be latched for the bank and will be incremented for every read of that bank,
until a new address for that bank is written to change the address pointer.
The bit description of the register is given in
Bit
31 to 3 -
2
1
0
Access
R/W
R/W
6
0
Symbol
ISO_BUF_
FILL
INT_BUF_
FILL
ATL_BUF_
FILL
Buffer Status register (address 0334h) bit description
reserved
Value
0000 0000h
R/W
5
0
Description
reserved
ISO Buffer Filled:
1 — Indicates one of the ISO PTDs is filled, and the ISO PTD area will be
processed.
0 — Indicates there is no PTD in this area. Therefore, processing of the ISO
PTDs will completely be skipped.
INT Buffer Filled:
1 — Indicates one of the INT PTDs is filled, and the INT PTD area will be
processed.
0 — Indicates there is no PTD in this area. Therefore, processing of the INT
PTDs will completely be skipped.
ATL Buffer Filled:
1 — Indicates one of the ATL PTDs is filled, and the ATL PTD area will be
processed.
0 — Indicates there is no PTD in this area. Therefore, processing of the ATL
PTDs will completely be skipped.
Rev. 04 — 4 February 2008
[1]
Description
ATL Done Timeout: This register determines the ATL done
time-out interrupt. This register defines the time-out in
milliseconds after which the ISP1760 asserts the INT line, if
enabled. It is applicable to ATL done PTDs only.
R/W
4
0
R/W
Table
3
0
Embedded Hi-Speed USB host controller
45.
ISO_BUF_
FILL
R/W
2
0
Table
INT_BUF_
FILL
R/W
44.
1
0
© NXP B.V. 2008. All rights reserved.
ISP1760
ATL_BUF_
FILL
R/W
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0
0