ISP1760ET STEricsson, ISP1760ET Datasheet - Page 68

• Manufacturer Part Number: ISP1760ET
• Manufacturer: STEricsson

Specifications of ISP1760ET

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 69.
[1]
[2]
Bit
DW7
DW5
DW3
DW1
Bit
DW6
DW4
DW2
DW0
Reserved.
EndPt[0].
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Status7[2:0]
[2]
A
INT_IN_5[3:0]
High-speed interrupt IN and OUT: bit allocation
H
Mult
[1:0]
9.3 High-speed interrupt IN and OUT
INT_IN_2[7:0]
reserved
reserved
Status6[2:0]
Table 69
INT_IN_7[11:0]
shows the bit allocation of the high-speed interrupt IN and OUT, periodic Transfer Descriptor (pTD).
MaxPacketLength[10:0]
DT
Status5[2:0]
Cerr
[1:0]
reserved
INT_IN_4[11:0]
Status4[2:0]
reserved
Status3[2:0]
INT_IN_1[11:0]
DataStartAddress[15:0]
Status2[2:0]
INT_IN_6[11:0]
S
Status1[2:0]
Type
[1:0]
EP
NrBytesTransferred[14:0] (32 kB
NrBytesToTransfer[14:0]
Token
INT_IN_3[11:0]
[1:0]
Status0[2:0]
9
8
DeviceAddress[6:0]
7
INT_IN_0[11:0]
6
1 B for high-speed)
5
INT_IN_5[11:4]
Frame[7:0]
4
SA[7:0]
3
INT_IN_2[11:8]
EndPt[3:1]
2
[1]
1
V
0