NH82801IR S LA9N Intel, NH82801IR S LA9N Datasheet - Page 16

• Manufacturer Part Number: NH82801IR S LA9N
• Manufacturer: Intel

Specifications of NH82801IR S LA9N

• Lead Free Status / RoHS Status: Compliant

11.
Problem:
Implication:
Workaround: Available
Status:
16
Note: There are no functional implications if the pin is configured as GPIO12.
ICH9M LAN_PHY_PWR_CTRL Functionality
LAN_PHY_PWR_CTRL output is driven low by the ICH9M A3 during a host reset with or
without power cycle for up to 3 RTC clock cycles due to the pin momentarily being
configured as an output GPIO.
Functional failures such as system hangs or link loss with dropped packets have been
observed when LAN_PHY_PWR_CTRL is tied to the LAN_DISABLE_N pin on the Intel®
82567.
ME-Enabled Platforms: An ME FW workaround will be provided with Mobile ME FW
Production Candidate release.
Non ME-Enabled Platforms: Remove LAN_PHY_PWR_CTRL Support on the Platform
No Fix. For steppings affected, see the Summary Table of Changes.
• LAN_PHY_PWR_CTRL functionality requires a soft strap setting in the SPI descriptor
• Both the ME Disable bits in the SPI flash descriptor (ICHSTRP0 bit 0 & MCHSTRP0
• MCHSTRP0 bit 7 in the SPI flash descriptor can be set to disable all other ME FW
• Isolate the LAN_PHY_PWR_CTRL signal from the LAN_DISABLE_N pin.
• LAN_DISABLE_N has a weak integrated pull-up resistor and the Intel 82567 PHY
and use of the integrated LAN controller in ICH9M with the Intel® 82567 PHY.
bit 0) must be set to 0 to enable the ME FW workaround.
based features, while keeping the ME FW workaround enabled.
will always remain enabled with this implementation.
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Specification Update
Errata