NH82801IR S LA9N Intel, NH82801IR S LA9N Datasheet - Page 21

• Manufacturer Part Number: NH82801IR S LA9N
• Manufacturer: Intel

Specifications of NH82801IR S LA9N

• Lead Free Status / RoHS Status: Compliant

Documentation Changes
9.
10.
11.
Specification Update
Make Correction to Table 5-40
Make the following correction to Table 5-4 7-3 in Section 5.13.14 Reset Behavior in the
Datasheet.
Table 5-40 Causes of Host and Global Resets
Update bit definition for Second_TO_STS
Update the following bit definition for Second_TO_STS in Section 13.9.5 TCO2_STS -
TCO2 Status Register in the Datasheet.
Correct Typo for ICH9M-SFF package ball AC22
Update the following ball designation for ICH9M-SFF package ball AC22 in Figure 6-6
and Table 6-3 and remove the wording “Preliminary” from the title of Figures 6-5 and
6-6 in the Datasheet.
ICH9 Mobile
Base
ICH9 Mobile
Enhanced
Power Failure: PWROK signal or VRMPWRGD signal
goes inactive or RSMRST# asserts
Component
Bit
Name
1
SECOND_TO_STS — R/WC.
0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.
1 = ICH10 sets this bit to 1 to indicate that the TIMEOUT bit
timeout
ICH10 will reboot the system after the second timeout. The reboot is done by
asserting PLTRST#.
Short Name
Trigger
ICH9M-E
ICH9M
occurred.
If this bit is set and the NO_REBOOT config bit is 0, then the
AHCI
Storage Technology
Yes
Yes
Intel
®
Description
Matrix
0/1 Support
No
Host Reset
without
RAID
Power
Cycle
Yes
No
Yes
Management Technology
with Power
Host Reset
Cycle
Intel
is
set and a second
®
Yes
No
Active
Power Cycle
Yes (Note 2)
Reset with
Global
21