NH82801IR S LA9N Intel, NH82801IR S LA9N Datasheet - Page 23

• Manufacturer Part Number: NH82801IR S LA9N
• Manufacturer: Intel

Specifications of NH82801IR S LA9N

• Lead Free Status / RoHS Status: Compliant

Documentation Changes
13.
Specification Update
4.
5.
6.
7.
Correct PCI Express* DSTS register definition for bit 1 (NFED)
Update the bit definition for bit 1(NFED) in Section 20.1.27 DTST- Device Status
Register Description in the Datasheet to match PCI Express* Base Specification
Revision 1.1.
Section 20.1.27 DSTS—Device Status Register
Address Offset: 4Ah–4Bh
Default Value:
Bit
1
power (PWROK low) or a Power Button Override event will result in the Intel ICH9 driving a
pin to a logic 1 to another device that is powered down.
The functionality that is multiplexed with the GPIO may not be utilized in desktop
configuration.
This GPIO is not an open-drain when configured as an output.
SPI_CS1#
When this signal is configured as GPO the output stage is an open drain.
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Non-Fatal Error Detected (NFED) — R/WC. Indicates a non-fatal error was detected.
0 = Non-fatal has not occurred.
1 = A non-fatal error occurred.
and CLGPIO6 (Digital Office Only) are
0010h
§ §
Description
Attribute:
Size:
located in the VccCL3_3 well.
R/WC, RO
16 bits
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