JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 27

• Manufacturer Part Number: JG82845 S L8D8
• Manufacturer: Intel

Specifications of JG82845 S L8D8

• Lead Free Status / RoHS Status: Compliant

Intel
®
82845 MCH for SDR Datasheet
R
NOTE: PCIRST# from the ICH2 is connected to RSTIN# and is used to reset AGP interface logic within the
G_DEVSEL#
G_REQ#
G_GNT#
G_AD[31:0]
G_C/BE[3:0]#
G_PAR
Signal Name
MCH. The AGP agent will also use PCIRST# provided by the ICH2 as an input to reset its internal
logic.
Type
AGP
AGP
AGP
AGP
AGP
AGP
s/t/s
I/O
I/O
I/O
I/O
O
I
Device Select: This signal indicates that a FRAME#-based AGP target
device has decoded its address as the target of the current access. The
MCH asserts G_DEVSEL# based on the DRAM address range being
accessed by a PCI initiator. As an input it indicates whether any device
on the bus has been selected.
Request: Indicates that a FRAME# or PIPE#-based AGP master is
requesting use of the AGP interface. This signal is an input into the
MCH.
Grant: During SBA, PIPE# and FRAME# operation, G_GNT#, along with
the information on the ST[2:0] signals (status bus), indicates how the
AGP interface will be used next.
Address/Data Bus: These signals are used to transfer both address and
data on the AGP interface.
Command/Byte Enable:
During FRAME# Operation: During the address phase of a transaction,
G_C/BE[3:0]# define the bus command. During the data phase,
G_C/BE[3:0]# are used as byte enables. The byte enables determine
which byte lanes carry meaningful data.
During PIPE# Operation: When an address is enqueued using PIPE#,
the G_C/BE# signals carry command information. The command
encoding used during PIPE#-based AGP is DIFFERENT than the
command encoding used during FRAME#-based AGP cycles (or
standard PCI cycles on a PCI bus).
Parity:
During FRAME# Operations: This signal is driven by the MCH when it
acts as a FRAME#-based AGP initiator during address and data phases
for a write cycle, and during the address phase for a read cycle. PAR is
driven by the MCH when it acts as a FRAME#-based AGP target during
each data phase of a FRAME#-based AGP memory read cycle. Even
parity is generated across AD[31:0] and G_C/BE[3:0]#.
During SBA and PIPE# Operation: This signal is not used during SBA
and PIPE# operation.
Description
Signal Description
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