JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 5

• Manufacturer Part Number: JG82845 S L8D8
• Manufacturer: Intel

Specifications of JG82845 S L8D8

• Lead Free Status / RoHS Status: Compliant

4
5
Intel
®
82845 MCH for SDR Datasheet
R
System Address Map.........................................................................................................97
4.1
4.2
4.3
4.4
4.5
Functional Description .....................................................................................................107
5.1
5.2
Memory Address Ranges .....................................................................................97
AGP Memory Address Ranges...........................................................................102
System Management Mode (SMM) Memory Range...........................................103
I/O Address Space..............................................................................................105
Intel
System Bus .........................................................................................................107
System Memory Interface ...................................................................................109
3.6.11
3.6.12
3.6.13
3.6.14
3.6.15
3.6.16
3.6.17
3.6.18
3.6.19
3.6.20
3.6.21
3.6.22
3.6.23
3.6.24
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.2.1
4.3.1
4.3.2
4.5.1
4.5.2
5.1.1
5.1.2
5.1.3
5.2.1
5.2.2
5.2.3
5.2.4
®
MCH Decode Rules and Cross-Bridge Address Mapping.........................105
SBUSN1—Secondary Bus Number Register (Device 1) ......................86
SUBUSN1—Subordinate Bus Number Register (Device 1)..................86
SMLT1—Secondary Master Latency Timer Register (Device 1) .........87
IOBASE1—I/O Base Address Register (Device 1) ...............................88
IOLIMIT1—I/O Limit Address Register (Device 1) ................................88
SSTS1—Secondary PCI-PCI Status Register (Device 1) .....................89
MBASE1—Memory Base Address Register (Device 1) ........................90
MLIMIT1—Memory Limit Address Register (Device 1) .........................90
PMBASE1—Prefetchable Memory Base Address
Register (Device 1)................................................................................91
PMLIMIT1—Prefetchable Memory Limit Address
Register (Device 1)................................................................................91
BCTRL1—PCI-PCI Bridge Control Register (Device 1) ........................92
ERRCMD1—Error Command Register (Device 1) ...............................93
DWTC—DRAM Write Thermal Management Control
Register (Device 1)................................................................................94
DRTC—DRAM Read Thermal Management Control
Register (Device 1)................................................................................95
VGA and MDA Memory Space..............................................................99
PAM Memory Spaces..........................................................................100
ISA Hole Memory Space .....................................................................100
TSEG SMM Memory Space ................................................................101
IOAPIC Memory Space .......................................................................101
System Bus Interrupt APIC Memory Space ........................................101
High SMM Memory Space...................................................................101
AGP Aperture Space (Device 0 BAR) .................................................102
AGP Memory and Prefetchable Memory.............................................102
Hub Interface Subtractive Decode ......................................................102
AGP DRAM Graphics Aperture ...........................................................103
SMM Space Definition .........................................................................104
SMM Space Restrictions .....................................................................104
Hub Interface Decode Rules ...............................................................105
AGP Interface Decode Rules ..............................................................106
Dynamic Bus Inversion........................................................................107
System Bus Interrupt Delivery .............................................................108
Upstream Interrupt Messages .............................................................108
Single Data Rate (SDR) SDRAM Interface Overview .........................109
Memory Organization and Configuration.............................................109
5.2.2.1
Memory Address Translation and Decoding .......................................111
DRAM Performance Description .........................................................112
5.2.4.1
Configuration Mechanism For DIMMs ...............................110
Data Integrity (ECC)...........................................................112
5