JG82845 S L8D8 Intel, JG82845 S L8D8 Datasheet - Page 42

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JG82845 S L8D8

Manufacturer Part Number
JG82845 S L8D8
Description
Manufacturer
Intel
Datasheet

Specifications of JG82845 S L8D8

Lead Free Status / RoHS Status
Compliant
Register Description
3.4.6
42
RCVENSTR—Strength Control Register (RCVENOUT
Signal Group)
Memory Address Offset:
Default Value:
Access:
Size:
This register controls the drive strength of the I/O buffers for the Receive Enable Out signal group
(RDCLKO# signal).
7:3
2:0
Bit
Reserved.
Receive Enable Out Signal Group (RCVEnOut) Strength Control. This field selects the
signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
34h
00h
R/W
8 bits
Descriptions
Intel
®
82845 MCH for SDR Datasheet
R

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