LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 114

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

The LPC47N227 supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. The
PCI_CLK, SER_IRQ and nCLKRUN pins are used for this interface. The Serial IRQ/CLKRUN Enable
bit D7 in CR29 activates the serial interrupt interface.
Timing Diagrams For SER_IRQ Cycle
A)
Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI
bridge hierarchy in a synchronous bridge design.
B)
Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
Note 1: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
around clock of the Stop Frame.
PCI_CLK
SER_IRQ
PCI_CLK
SER_IRQ
Drive Source
Driver
Start Frame timing with source sampled a low pulse on IRQ1
Stop Frame Timing with Host using 17 SER_IRQ sampling period
S
FRAME
None
IRQ14
R
IRQ
SL
or
H
T
START
S
Host Controller
IRQ15
START FRAME
H
IRQ15
FRAME
R
1
T
SERIAL IRQ
R
S
IOCHCK#
None
FRAME
114
R
T
IRQ0 FRAME IRQ1 FRAME
T
S
None
I
R
2
STOP FRAME
Host Controller
T
STOP
H
S
IRQ1
1
R
R
T
T
NEXT CYCLE
IRQ2 FRAME
S
None
START
R
T
3