LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 17

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface
The
implementation of the LPC bus.
LPC Cycles
The following cycle types are supported by the
LPC protocol.
The LPC47N227 ignores cycles that it does not
support.
Field Definitions
The data transfers are based on specific fields
that
depending on the cycle type. These fields are
driven onto the LAD[3:0] signal lines to
communicate
information over the LPC bus between the host
and the LPC47N227.
LAD[3:0]
nLFRAME
nPCI_RESET
nLDRQ
nIO_PME
nLPCPD
SER_IRQ
PCI_CLK
nCLKRUN
CYCLE TYPE
I/O Write
I/O Read
DMA Write
DMA Read
SIGNAL NAME
are
following
used
address,
sub-sections
in
TRANSFER SIZE
1 Byte
1 Byte
1 Byte
1 Byte
Input
Output
OD
Input
Input
various
I/O
Input
I/O
I/OD
TYPE
control
See the Low Pin
combinations,
specify
and
data bus.
broken cycle
Encoded DMA/Bus Master request for the LPC interface.
wakeup.
prepare for power to be shut on the LPC interface.
PCI Clock.
PCI_CLK be started.
LPC address/data bus. Multiplexed command, address and
Frame signal. Indicates start of new cycle and termination of
PCI Reset. Used as LPC Interface Reset.
Power Mgt Event signal. Allows the LPC47N227 to request
Powerdown Signal. Indicates that the LPC47N227 should
Serial IRQ.
Clock Run. Allows the LPC47N227 to request the stopped
data
the
17
LPC Interface Signal Definition
The signals required for the LPC bus interface
are described in the table below.
signals
characteristics.
Count (LPC) Interface Specification Revision 1.0
from Intel, Section 4.2 for definition of these
fields.
nLFRAME Usage
nLFRAME is used by the host to indicate the
start of cycles and the termination of cycles due
to an abort or time-out condition. This signal is
to be used by the LPC47N227 to know when to
monitor the bus for a cycle.
This signal is used as a general notification that
the LAD[3:0] lines contain information relative to
the start or stop of a cycle, and that the
LPC47N227 monitors the bus to determine
whether the cycle is intended for it. The use of
nLFRAME allows the LPC47N227 to enter a
lower power state internally. There is no need
for the LPC47N227 to monitor the bus when it is
inactive, so it can decouple its state machines
from the bus, and internally gate its clocks.
When the LPC47N227 samples nLFRAME
active, it immediately stops driving the LAD[3:0]
signal lines on the next clock and monitor the
bus for new cycle information.
DESCRIPTION
use
PCI
33MHz
electrical
LPC bus
signal