LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 132

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

NAME/DEFAULT
PME_EN1
Default = 0x00
PME_EN2
Default = 0x00
on VTR POR
on VTR POR
REGISTER
OFFSET
(R/W)
(R/W)
05
06
PME Wake Enable Register 1
This register is used to enable individual LPC47N227
PME wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake
event so that the associated status bit is “1” and the
PME_En bit is “1”, the source will assert the nIO_PME
signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status register
will indicate the state of the wake source but will not
assert the nIO_PME signal.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
PME Wake Enable Register 2
This register is used to enable individual LPC47N227
PME wake sources onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake
source is active (“1”), if the source asserts a wake
event so that the associated status bit is “1” and the
PME_En bit is “1”, the source will assert the nIO_PME
signal.
When the PME Wake Enable register bit for a wake
source is inactive (“0”), the PME Wake Status register
will indicate the state of the wake source but will not
assert the nIO_PME signal.
Bit[0] RI1
Bit[1] RI2
Bit[2] GP20
Bit[3] GP21
Bit[4] GP22
Bit[5] GP23
Bit[6] GP24
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
132
DESCRIPTION