LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 124

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Note: FIGURE 5 is for illustration purposes only and in not intended to suggest specific implementation
details.
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either
the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is
programmed as an input has no effect (Table 51).
When a GPIO port is programmed as an output, the logic value or the inverted logic value that has
been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is
programmed as an output returns the last value written to the data register (Table 51).
The LPC47N227 provides 21 GPIOs that can directly generate a PME. See the table in the next
section. The GPIO Polarity Registers in the Configuration section select the edge on these GPIO pins
that will set the associated status bit in the PME_STS1 – PME_STS3 registers. The default is the low-
to-high edge. If the corresponding enable bit in the PME_EN1 – PME_EN3 registers and the PME_EN
bit in the PME_EN register is set, a PME will be generated. These registers are located in the Runtime
Registers Block, which is located at the address contained in the configuration registers CR30. The
GPx Write
GPx Read
HOST OPERATION
SD-bit
WRITE
READ
Data Register
Transparent
D-TYPE
Q
D
Bit-n
GPIO
Q
D
FIGURE 5 - GPIO FUNCTION ILLUSTRATION
Table 51 – GPIO Read/Write Behavior
NO EFFECT
LATCHED VALUE OF GPIO PIN LAST WRITE TO GPIO DATA
0
1
GPIO INPUT PORT
124
GPIO
Configuration
Register bit-1
(Polarity)
REGISTER
BIT PLACED IN GPIO DATA
REGISTER
GPIO OUTPUT PORT
GPIO
Configuration
Register bit-0
(Input/Output)
GPIO
PIN