LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 145

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR05 can only be accessed in the configuration state and after the CSR has been initialized to 05H.
Note
Note
FDC OUTPUT
BIT NO.
1
2
CONTROL
:
:
(CR05.1)
1
4,3
6,7
0
2
5
1,2
1
Bits CR05[1:0] do not affect the Parallel Port FDC.
In the LPC47N227, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC
Output Control CR05.1 (Table 62). If the FDC Output Control is active DRVDEN1 will behave
as follows if CR03.4 is 0 the DRVDEN1 output pin assumes the value of the DRVDEN1
function, if CR03.4 is 1 the DRVDEN1 output pin stays high. If the FDC Output Control is
inactive the DRVDEN1 Control will have no affect on the DRVDEN1 output pin.
0
0
1
FDC Output Type
Control
(R/W)
FDC Output
Control
(R/W)
FDC DMA Mode
DenSel
Swap Drives 0,1
Reserved
Type: R/W
BIT NAME
CONTROL
DRVDEN1
(CR03.4)
0
1
X
Table 62 – DRVDEN1 Control
0 = FDC Outputs are open drain (default).
1 = FDC Outputs are push-pull.
0 = FDC Outputs Active (default).
1 = FDC Outputs Tri-State.
0 = Burst mode is enabled for the FDC FIFO execution phase data
transfers (default).
1 = Non-Burst mode enabled.
0= do not swap (default).
1= swap drives and motor select 0 and 1 of the FDC on the
parallel port.
Read Only. A read returns 0.
Floppy Disk Setup Register
BIT 4
Table 61 – CR05
DRVDEN1
TRISTATE
0
0
1
1
(PIN 2)
1/0
1
145
NORMAL DRVDEN1 FUNCTION
DRVDEN1 FORCED HIGH
ALL FDD OUTPUT PINS ARE
TRISTATED
BIT 3
DESCRIPTION
Default: 0x00 on VCC POR
0
1
0
1
DESCRIPTION
DENSEL OUTPUT
Normal (default)
Reserved
1
0