ISP1183BS STEricsson, ISP1183BS Datasheet
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ISP1183BS
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... If you have any questions related to the document, please contact our nearest sales office or wired.support@stericsson.com. Thank you for your cooperation and understanding. ...
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ISP1183 Low-power USB Peripheral Controller with DMA Rev. 03 — 20 January 2009 1. General description The ISP1183 is a Universal Serial Bus (USB) Peripheral Controller that complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed ...
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... Printer Scanner 4. Ordering information Table 1. Ordering information Type number Package Name Description ISP1183BS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 × 5 × 0. SoftConnect is a trademark of ST-NXP Wireless. ISP1183_3 Product data sheet Low-power USB Peripheral Controller with DMA Rev. 03 — ...
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USB 6 MHz BUS XTAL1 XTAL2 MHz PLL 3.3 V OSCILLATOR 1.5 kΩ 12 MHz SoftConnect ...
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... DGND XTAL1 XTAL2 V BUS DM DP ISP1183_3 Product data sheet Low-power USB Peripheral Controller with DMA terminal 1 index area 1 INT_N 2 CS_N WR_N 3 RD_N 4 ISP1183BS DGND 5 6 XTAL1 GND 7 XTAL2 (exposed die pad BUS Transparent top view Pin description [2] Pin Type Description 1 O interrupt output; active LOW 3 ...
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Table 2. [1] Symbol AGND V REG(3V3) VBUSDET_ N DREQ DACK RESET_N A0 V DD(I/O) DATA0 DATA1 VOUT3V3 DGND DATA2 DATA3 DGND DATA4 DATA5 ISP1183_3 Product data sheet Low-power USB Peripheral Controller with DMA Pin description …continued [2] Pin Type ...
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Table 2. [1] Symbol DATA6 DATA7 V DD(I/O) WAKEUP SUSPEND GND [1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. [ input output; I/O = input/output; AI/O = analog input/output. ISP1183_3 ...
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Functional description The ISP1183 is a full-speed USB Peripheral Controller with configurable endpoints. It has a fast general-purpose parallel interface for communication with many types of microcontrollers and microprocessors. It supports an 8-bit data bus with ...
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Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 × over-sampling principle. It can track jitter and frequency drift as specified in Universal Serial Bus Specification Rev. 2.0. ...
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Table 3. Pin name SUSPEND VBUSDET_N DATA [1] Not driven to LOW. There is, however, no current flow through pads because no I/O supply voltage is available. Therefore, no potential will develop at the output. [2] During the normal operation, ...
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Fig 5. Typical oscillator circuit The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. In the suspend state, the crystal oscillator and the PLL are switched off to save power. The oscillator operation is controlled ...
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Stable external clock available at A. Fig 7. Clock with respect to the external POR A hardware reset disables all USB endpoints and clears all Endpoint Configuration Registers (ECRs), except for the control endpoint that is fixed and always enabled. ...
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Interrupt Enable register reset interrupt source IERST suspend interrupt source IESUSP IERESM IESOF IEP14 ... IEP0IN EPn interrupt source IEP0OUT Fig 8. Interrupt logic Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the Interrupt register is read. ...
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Endpoint description Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the host and the device. At design time, each endpoint is assigned a unique number (endpoint ...
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Table 5. FFOSZ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each programmable FIFO can independently be configured through its ECR. The total physical size of all enabled endpoints (IN plus OUT), ...
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When reset by hardware or through the USB bus, the ISP1183 disables all endpoints and clears all ECRs, except for the control endpoint, which is fixed and always enabled. Endpoint initialization can be done at any time. It is, however, ...
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DMA transfer Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without intervention of the CPU. Many implementations of DMA exist. The ISP1183 supports two methods: • 8237 compatible ...
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DMA mode is selected by clearing bit DAKOLY in the Hardware Configuration register (see Table 8. Table 8. Symbol DREQ DACK RD_N WR_N The DMA subsystem of an IBM-compatible PC is based on the ...
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The ISP1183 places the byte or word to be transferred on data bus lines because its RD_N signal was asserted by the 8237. 8. The 8237 waits one DMA clock period and then de-asserts MEMW_N and IOR_N. This latches ...
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Fig 10. ISP1183 in DACK-only DMA mode 10.4 EOT conditions 10.4.1 Bulk endpoints A DMA transfer to or from a bulk endpoint can be terminated by any of the following conditions (for bit names, see the DMA Function and Scratch ...
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Table 10. EOT condition DMA Counter register Short packet DMAEN bit in the DMA Function and Scratch register [1] The DMA transfer stops. No interrupt, however, is generated. 10.4.2 Isochronous endpoints A DMA transfer to or from an isochronous endpoint ...
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Suspend and resume 11.1 Suspend conditions The ISP1183 detects a USB suspend status when a constant idle state is present on the USB bus for more than 3 ms. The bus-powered devices that are suspended must not consume more ...
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A USB bus INT_N GOSUSP WAKEUP SUSPEND Fig 11. Suspend and resume timing In Figure 11: • A: indicates the point at which the USB bus enters the idle state. • B: indicates resume condition, which can ...
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Resume conditions A wake-up from the suspend state is initiated either by the USB host or by the application: • USB host: drives a K-state on the USB bus (global resume). • Application: remote wake-up through a HIGH level ...
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Commands and registers The functions and registers of the ISP1183 are accessed using commands, which consist of a command code, followed by optional data bytes (read or write action). An overview of the available commands and registers is given ...
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Table 13. Command and register overview Name Destination Data flow commands Write Control OUT Buffer illegal: endpoint is read-only Write Control IN Buffer FIFO endpoint 0 IN Write Endpoint n Buffer (n = FIFO endpoints (IN 1 ...
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Table 13. Command and register overview Name Destination DMA commands Write or read DMA Function DMA Function and Scratch and Scratch register register Write or read DMA DMA Configuration Configuration register Write or read DMA Counter DMA Counter register General ...
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Code: 30h to 3Fh — read (control OUT, control IN, endpoints 1 to 14) Transaction — write or read 1 byte Table 14. Endpoint Configuration register: bit allocation Bit 7 6 Symbol FIFOEN EPDIR [1][2] Reset 0 0 Access R/W ...
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Mode register (R/W: B9h/B8h) This command accesses the ISP1183 Mode register, which consists of 1 byte (bit allocation: see The Mode register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be ...
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Table 20. Hardware Configuration register: bit allocation Bit 15 14 Symbol reserved EXTPUL Reset 0 0 Access R/W R/W Bit 7 6 Symbol DAKOLY DRQPOL Reset 0 1 Access R/W R/W Table 21. Bit Symbol EXTPUL 13 ...
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Transaction — write or read 4 bytes Table 22. Interrupt Enable register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R/W R/W Bit 23 22 Symbol IEP14 IEP13 Reset 0 0 Access R/W R/W Bit 15 14 Symbol ...
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Table 23. Bit 12.1.6 Reset Device (F6h) This command resets the ISP1183 in the same way as an external hardware reset through input RESET_N. All registers are initialized to their reset values. Code: F6h — reset the ...
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Table 24. Byte # (8-bit bus Table 25. A0 HIGH LOW LOW LOW LOW LOW LOW : Remark: There is no protection against writing or reading past a buffer’s boundary, against writing ...
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Table 27. Bit Symbol 7 EPSTAL 6 EPFULL1 5 EPFULL0 4 DATA_PID 3 OVERWRITE This bit is set by hardware. Logic 1 indicates that a new set-up packet has 2 SETUPT 1 CPUBUF 0 - 12.2.3 Stall or Unstall Endpoint ...
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Code: 61h to 6Fh — validate endpoint buffer (control IN, endpoints 1 to 14) Transaction — none 12.2.5 Clear Endpoint Buffer (70h, 72h to 7Fh) This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception ...
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Table 29. Bit Symbol 2 SETUPT 1 CPUBUF 0 - 12.2.7 Acknowledge Setup (F4h) This command acknowledges to the host that a SETUP packet was received. The arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands ...
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DMA Configuration register (R/W: F1h/F0h) This command defines the DMA configuration of the ISP1183 and enables or disables DMA transfers. The command accesses the DMA Configuration register, which consists of 2 bytes. The bit allocation is given in disabled), ...
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The internal DMA counter is automatically reloaded from the DMA Counter register when DMA is re-enabled (DMAEN = 1). For details, see Code: F2h/F3h — write or read DMA Counter register Transaction — write or read 2 bytes Table 34. ...
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Table 38. Error code (binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 12.4.2 Unlock Device (B0h) This command unlocks the ISP1183 from write-protection mode after a resume. In the suspend state, ...
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Table 40. Bit 12.4.3 Frame Number register (R: B4h) This command returns the frame number of the last successfully received SOF followed by reading one or two bytes from the Frame Number register, containing the ...
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Table 44. Chip ID register: bit allocation Bit 15 14 Symbol Reset Access R R Bit 7 6 Symbol Reset Access R R Table 45. Bit 12.4.5 Interrupt register (R: C0h) This command indicates ...
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Table 47. Bit Symbol EP14 22 EP13 21 EP12 20 EP11 19 EP10 18 EP9 17 EP8 16 EP7 15 EP6 14 EP5 13 EP4 12 EP3 11 EP2 10 EP1 9 EP0IN 8 EP0OUT ...
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Limiting values Table 48. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V bus supply voltage BUS V I/O supply voltage DD(I/O) V input voltage I I latch-up current lu V electrostatic discharge ...
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Static characteristics Table 50. Static characteristics: supply pins BUS DD(I/O) Symbol Parameter V 3.3 volt regulator voltage REG(3V3) I supply current CC I suspend ...
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Table 52. Static characteristics: analog I/O pins DP and BUS DD(I/O) Symbol Parameter Input levels V differential input sensitivity DI V differential common mode ...
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Dynamic characteristics Table 53. Dynamic characteristics BUS DD(I/O) Symbol Parameter Reset t external RESET_N pulse width crystal oscillator running W(RESET_N) Crystal oscillator f frequency ...
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Timing 16.1.1 Parallel I/O timing Table 55. Dynamic characteristics: parallel interface timing 2 3 BUS REG(3V3) DD(I/O) Symbol Parameter Read timing (see Figure 13) t address hold time after RD_N HIGH ...
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AVRL A0 t SLRL CS_N t RLRH RD_N t RLDV DATA (1) If required, CS_N can be kept permanently asserted. There is no need to de-assert and assert in between the read and write cycles. Fig 13. Parallel interface ...
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Table 56. Dynamic characteristics: access cycle timing 2 3 BUS REG(3V3) DD(I/O) Symbol Parameter T cycle time for write data, then write command cy(WD-WC) Write command + read data (see Figure 17 ...
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DATA WR_N RD_N CS_N (1) Example: read data. Fig 18. Read data + write command cycle timing 16.1.3 DMA timing: single-cycle mode Table 57. Dynamic characteristics: single-cycle DMA timing 2 3 BUS ...
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DREQ DACK DATA Fig 20. DMA read timing in DACK-only mode DREQ DACK DATA Fig 21. DMA write timing in DACK-only mode 16.1.4 DMA timing: burst mode Table 58. Dynamic characteristics: burst mode DMA timing 2.7 ...
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DREQ DACK RD_N, WR_N Fig 22. Burst mode DMA timing 17. Application information 17.1 Bus-powered mode In bus-powered mode, pin VBUSDET_N is not necessary. See MCU Fig 23. Bus-powered mode 17.2 Hybrid-powered mode In this mode: • When the USB ...
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Fig 24. Hybrid-powered mode 17.3 Self-powered mode In self-powered mode, pin VBUSDET_N cannot be used. The V in the following two ways: • Connecting V – When VBUSDET goes LOW, the microprocessor clears bit SOFTCT. – When VBUSDET goes HIGH, ...
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MCU DM V BUS Fig 25. V MCU BUS Fig 26. Transistor switching ISP1183_3 Product data sheet Low-power USB Peripheral Controller with DMA V CC VBUSDET ISP1183 22 Ω Ω 100 ...
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Test information The dynamic characteristics of the analog I/O ports (DP and DM) as listed in were determined using the circuit shown in Load capacitance: (1) C Speed: (1) Full-speed mode only: internal 1.5 kΩ pull-up resistor on DP ...
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Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS ...
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Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 20.1 Introduction to soldering Soldering ...
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Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, ...
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MSL: Moisture Sensitivity Level Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 21. Abbreviations Table 61. Acronym ACK ACPI AT CMOS CRC ...
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Table 61. Acronym PIO PLL POR PSOF RISC SIE SOF USB ISP1183_3 Product data sheet Low-power USB Peripheral Controller with DMA Abbreviations …continued Description Parallel I/O Phase-Locked Loop Power-On Reset Pseudo Start-Of-Frame Reduced Instruction Set Computer Serial Interface Engine Start-Of-Frame ...
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Revision history Table 62. Revision history Document ID Release date ISP1183_3 20090120 • Modifications: Globally changed NXP Semiconductors and NXP to ST-NXP Wireless. Also updated the legal text. • Section 17.3 “Self-powered ISP1183_2 20070607 ISP1183-01 20040224 (9397 750 11804) ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration HVQFN32 . ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Wave and reflow soldering . . . . . . . . . . . . . . . 56 20.3 Wave soldering . . . . . . . . . . . . . . . . ...
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Information in this document is provided solely in connection with ST-NXP products. ST-NXP Wireless NV and its subsidiaries (“ST-NXP”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...