ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 25

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

Table 13.
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CD00222684
Product data sheet
Name
Check Control IN Status
Check Endpoint n Status
(n = 1 to 14)
Acknowledge Setup
General commands
Read Control OUT Error Code
Read Control IN Error Code
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read Scratch Register
Read Frame Number
Read Chip ID
Read Interrupt Register
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
In 8-bit bus mode this command requires more time to complete than other commands. See
During isochronous transfer in 16-bit mode, because N ≤ 1023, the firmware must take care of the upper byte.
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1181B.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1181B.
Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
Command and register summary
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12.1.1 Write/Read Endpoint Configuration
12.1 Initialization commands
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Initialization commands are used during the enumeration process of the USB network.
These commands are used to configure and enable the embedded endpoints. They also
serve to set the USB assigned address of ISP1181B and to perform a device reset.
This command is used to access the Endpoint Configuration Register (ECR) of the target
endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN),
FIFO size and buffering scheme. It also enables the endpoint FIFO. The register bit
allocation is shown in
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization sequence
and be configured with their default values (see
when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration which affects the allocated
memory (size, enable/disable), the FIFO memory contents of all endpoints becomes
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Destination
Endpoint Status Image Register
endpoint 0 IN
Endpoint Status Image Register n
endpoint 1 to 14
Endpoint 0 IN and OUT
Error Code Register
endpoint 0 OUT
Error Code Register endpoint 0 IN
Error Code Register
endpoint 1 to 14
all registers with write access
Scratch Register
Frame Number Register
Chip ID Register
Interrupt Register
…continued
Table
Rev. 05 — 25 August 2010
14. A bus reset will disable all endpoints.
F4
B0
B2/B3
B4
C0
Code (Hex)
D1
D2 to DF
A0
A1
A2 to AF
B5
Table
Full-speed USB peripheral controller
4). Automatic FIFO allocation starts
Table
58.
Transaction
read 1 byte
read 1 byte
-
read 1 byte
read 1 byte
read 1 byte
write 2 bytes
write/read 2 bytes
read 1 or 2 bytes
read 2 bytes
read 4 bytes
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© ST-ERICSSON 2010. All rights reserved.
ISP1181B
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