ISP1181BBSUM STEricsson, ISP1181BBSUM Datasheet - Page 34

• Manufacturer Part Number: ISP1181BBSUM
• Manufacturer: STEricsson

Specifications of ISP1181BBSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

CD00222684
Product data sheet
12.2.3 Stall Endpoint/Unstall Endpoint
12.2.4 Validate Endpoint Buffer
Table 32.
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status Register (see
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can restall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also reinitialized. This flushes the buffer: if it is an OUT
buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoint 1 to 14)
Transaction — none
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the
buffer is valid and can be sent to the host, when the next IN token is received. For a
double-buffered endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint see
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none
Bit
7
6
5
4
3
2
1
0
Endpoint Status Register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE
SETUPT
CPUBUF
-
Rev. 05 — 25 August 2010
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled,
0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by an
Unstall Endpoint command. The endpoint is automatically unstalled
upon reception of a SETUP token.
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA PID, 1
= DATA1 PID).
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it was
acknowledged or before the endpoint was stalled. This bit is cleared
by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1 the
firmware must stop ongoing setup actions and wait for a new Setup
packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU access
(0 = primary buffer, 1 = secondary buffer).
reserved
Table
Full-speed USB peripheral controller
31).
Section
© ST-ERICSSON 2010. All rights reserved.
9.5.
ISP1181B
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