PSD834F2-15M STMicroelectronics, PSD834F2-15M Datasheet - Page 64

• Manufacturer Part Number: PSD834F2-15M
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-15M

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on PSD sig-
nals instead of having to scan the status out seri-
ally using the standard JTAG channel. See
Application Note AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed in the section entitled “Ready/Busy (PC3)”,
on page 15. TSTAT is High when the PSD device
is in READ Mode (primary and secondary Flash
memory contents can be read). TSTAT is Low
when Flash memory Program or Erase cycles are
in progress, and also when data is being written to
the secondary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from multiple PSD devices and a
wired-OR connection of TERR signals from those
Table 34. JTAG Enable Register
Note: 1. The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configu-
64/95
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(RESET)
ration bit (via PSDsoft Express). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG enable register is used
to enable the JTAG signals.
JTAG_Enable
X
X
X
X
X
X
X
pulse
0 = off JTAG port is disabled.
1 = on JTAG port is enabled.
0
0
0
0
0
0
0
is
received
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
after
an
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to '1.' The PSD
Configuration Register bits are set to '0.' The code,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.